Patent classifications
G05B2219/49034
DETERMINING WHETHER TO PRINT A THREE-DIMENSIONAL PRINT JOB
A method (2 analyses (4) a layer of a three-dimensional print job wherein the value of a parameter relating to the processing time of the layer is determined. The method (2) determines (6) whether the layer of the three-dimensional print job is to be printed in a three-dimensional printer. This determination is based on the value of the parameter relating to processing time.
PROTECTIVE STRUCTURES
Examples described herein relate to a system consistent with the disclosure. For instance, the system may comprise an additive manufacturing device including hardware to form a three-dimensional (3D) model, a memory resource, and a processing resource to receive data related to the 3D model, modify the data related to the 3D model to include a protective structure connected to the 3D model by a fusion bond, and dispense, based on the modified data, a printing agent onto build material layers to produce the 3D model and the protective structure around a portion of the 3D model.
OBJECT MODEL GENERATION
Object model data modification is described in which object model data defining a three dimensional model to be generated by a three-dimensional printer may be obtained. Data relating to a first sensitive portion of the model may be obtained, the first sensitive portion representing a portion of the model to be concealed. Modified object model data in generated, the modified object model data including a first version of the three dimensional model that is represented in a first pre-processing application without exposing the first sensitive portion, and including the first object model data defining the three dimensional model for printing by a three-dimensional printer.
INFORMATION PROCESSING APPARATUS, MEDIUM, INFORMATION PROCESSING METHOD, AND MODELING SYSTEM
An information processing apparatus for providing data for modeling to an additive manufacturing apparatus that models a modeling object by repeatedly stacking layers of material is provided. The information processing apparatus includes a volume calculation unit configured to calculate a volume of the modeling target and a support-part-modeling-method determination unit configured to determine a modeling method of a support part that supports the modeling target according to the volume.
INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SPECIFIC EXPECTED FAIL RATE
Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.
Integrated circuit chip reliability qualification using a sample-specific expected fail rate
Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.