A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

Disclosed is a low dropout linear voltage regulator and a control circuit thereof. The control circuit includes an error amplifier and a backflow prevention circuit, which compares an input voltage with an output voltage, to switch a substrate voltage and a voltage at a control terminal of the power transistor to a higher one of the input voltage and the output voltage, thus the power transistor and its parasitic diode can be turned off in time when the output voltage is greater than the input voltage, so as to prevent the power transistor from being damaged by current backflow and improve reliability of the low dropout linear regulator.

Disclosed is a low dropout linear voltage regulator and a control circuit thereof. The control circuit includes an error amplifier and a backflow prevention circuit, which compares an input voltage with an output voltage, to switch a substrate voltage and a voltage at a control terminal of the power transistor to a higher one of the input voltage and the output voltage, thus the power transistor and its parasitic diode can be turned off in time when the output voltage is greater than the input voltage, so as to prevent the power transistor from being damaged by current backflow and improve reliability of the low dropout linear regulator.

In an example, a circuit includes an input stage having a control voltage input, a feedback input, a first control output and a second control output. The feedback input is coupled to a driver output. A first path stage has a first voltage input and a third output. The first voltage input is coupled to the first control output, and the third output is coupled to the driver output. A second path stage has a second voltage input and a fourth output. The second voltage input is coupled to the second control output, and the fourth output is coupled to the driver output. A load transistor has a control input coupled to the driver output. The input stage is configured to provide gm-boosting to the first path stage to turn on the load transistor responsive to an output voltage at a voltage output.

In an example, a circuit includes an input stage having a control voltage input, a feedback input, a first control output and a second control output. The feedback input is coupled to a driver output. A first path stage has a first voltage input and a third output. The first voltage input is coupled to the first control output, and the third output is coupled to the driver output. A second path stage has a second voltage input and a fourth output. The second voltage input is coupled to the second control output, and the fourth output is coupled to the driver output. A load transistor has a control input coupled to the driver output. The input stage is configured to provide gm-boosting to the first path stage to turn on the load transistor responsive to an output voltage at a voltage output.

Certain aspects of the present disclosure provide a power supply system. The power supply system generally includes a first voltage regulator and a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system. The power supply system may also include a current balancer circuit configured to adjust an output current of the first voltage regulator based on determined headrooms of the first voltage regulator and the second voltage regulator.

Certain aspects of the present disclosure provide a power supply system. The power supply system generally includes a first voltage regulator and a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system. The power supply system may also include a current balancer circuit configured to adjust an output current of the first voltage regulator based on determined headrooms of the first voltage regulator and the second voltage regulator.

A voltage regulator comprising an error amplifier, a pass transistor and a buffer circuit arranged between the error amplifier and the pass transistor. The buffer circuit comprises a load detector configured to detect a load current of the regulator by monitoring an output signal of the error amplifier. The buffer circuit further comprises a load compensator configured to receive a load signal from the load detector. The load signal indicates the load of the regulator. The load compensator is further configured to change its output impedance based on the load signal such that variations of the load of the voltage regulator are compensated. There is additionally provided a corresponding system, a corresponding method and a corresponding design structure.

A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.