An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.

A timing generator, a timing generating method and an associated control chip are provided, wherein the timing generator includes a receiving circuit, a transmitting circuit coupled to the receiving circuit, and a control unit respectively coupled to the receiving circuit and the transmitting circuit. The receiving circuit may be configured to receive a timing data set from a storage device. The transmitting circuit may be configured to select a specific signal type within multiple signal types according to the timing data set, and output an output signal having the specific signal type with a specific time length, wherein the timing data set indicates the specific signal type and the specific time length. The control unit may be configured to control operations of the receiving circuit and the transmitting circuit.

The kernel function generation unit 81 defines a first kernel function by using two-dimensional feature representation that represents a combination of two features of data. The model learning unit 82 defines a linear model including an inner product of a mapping used in the first kernel function and a first weight and performs learning with the defined linear model. The component expanding unit 83 expands the learned linear model to define expanded component representation that is new component representation of the data. The expansion model generation unit 84 generates an expansion model including an inner product of data by the expanded component representation and a second weight.

The kernel function generation unit 81 defines a first kernel function by using two-dimensional feature representation that represents a combination of two features of data. The model learning unit 82 defines a linear model including an inner product of a mapping used in the first kernel function and a first weight and performs learning with the defined linear model. The component expanding unit 83 expands the learned linear model to define expanded component representation that is new component representation of the data. The expansion model generation unit 84 generates an expansion model including an inner product of data by the expanded component representation and a second weight.

Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.

Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.

A sequence signal generator and a sequence signal generation method are provided. In the sequence signal generation method, a waveform output instruction sent by a host computer is received to acquire waveform data. The waveform data includes original square wave sequence data and target square wave sequence data, and the target square wave sequence data includes a preliminary delay parameter and a secondary delay parameter. An original square wave sequence signal is acquired according to the original square wave sequence data. According to the preliminary delay parameter, preliminary delay processing is performed on the original square wave sequence signal to acquire an intermediate square wave sequence signal, and according to the secondary delay parameter, secondary delay processing is performed on the intermediate square wave sequence signal to acquire a target square wave sequence signal.