A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.

The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.

An unnecessary circuit operation in a clock enabler circuit accompanying toggling of a clock signal is suppressed. A state holding unit performs a holding operation of a state as to whether or not to output an output clock signal according to an internal clock signal. A clock signal output unit controls output of the output clock signal according to the state held in the state holding unit. A control unit supplies, to the state holding unit, the internal clock signal and a value of the state that are necessary for the holding operation in the state holding unit on a basis of a clock signal and a clock enable signal from an outside.

Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

Systems and methods are provided for master-to-master OT-based artifact peering. A “master-to-master” architecture for artifacts is implemented in a network comprising a plurality of nodes and clients, where no node is designated a “master” or “primary” for a given artifact. A first node receives a subset of remote proposed operations from a second node and determines if a conflict exists between the received subset of remote proposed operations and at least one of a plurality of locally-proposed operations. The first node resolves the conflict based on a total-ordering agreed upon between the first node and the second node. The first node transforms at least one operation, either received or locally-proposed, based on the resolved conflict. The first node than updates a local log to include the transformed operation.

Systems and methods are provided for master-to-master OT-based artifact peering. A “master-to-master” architecture for artifacts is implemented in a network comprising a plurality of nodes and clients, where no node is designated a “master” or “primary” for a given artifact. A first node receives a subset of remote proposed operations from a second node and determines if a conflict exists between the received subset of remote proposed operations and at least one of a plurality of locally-proposed operations. The first node resolves the conflict based on a total-ordering agreed upon between the first node and the second node. The first node transforms at least one operation, either received or locally-proposed, based on the resolved conflict. The first node than updates a local log to include the transformed operation.

An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.

An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.