Systems, methods, and devices are described for generating multi-tone waveforms. A count signal having a count value is generated. A plurality of step values and a plurality of phase values are received. For each increment of the count value, an index value corresponding to each step value of the plurality of step values is calculated based on the step value, the count value, and a respective phase value of the plurality of phase values. A tone point value corresponding to each calculated index value is determined to generate a plurality of tone point values for each increment of the count value. The determined tone point values are summed to generate a corresponding waveform point for each increment of the count value. A waveform is generated as a sequence of generated waveform points.

A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

Disclosed area channel circuit and an electronic device, including a power channel switch, a signal channel switch, a control module, and a comparison module. The power channel switch is connected between a circuit input end and a first circuit output end, and the signal channel switch is connected between the circuit input end and a second circuit output end. The comparison module is connected to the circuit input end and is configured to compare an input voltage with a specified voltage threshold, including a first voltage threshold, and feedback corresponding comparison results to the control module. The control module is configured to turn on the signal channel switch and turn off the power channel switch when the input voltage is lower than the first voltage threshold, and to turn on the signal channel switch when the input voltage is higher than the first voltage threshold.

A detection device for detecting types of a universal serial bus cable includes a detection circuit and a control unit. The detection circuit includes a signal source, a receiving end, a first resistor, a second resistor, a variable resistor, a first capacitor, a second capacitor, first through fourth switches, a V.sub.BUS end, an ID end, and a ground end. The signal source provides a detection signal. The control unit is electrically connected to the detection circuit, and is configured to control the first through the fourth switches according to a plurality of on-off states, to receive the detection signal and a V.sub.BUS signal from the receiving end in the plurality of on-off states, to generate a plurality of detection results, and to determine the type of the USB cable according to the plurality of detection results.

A detection device for detecting types of a universal serial bus cable includes a detection circuit and a control unit. The detection circuit includes a signal source, a receiving end, a first resistor, a second resistor, a variable resistor, a first capacitor, a second capacitor, first through fourth switches, a V.sub.BUS end, an ID end, and a ground end. The signal source provides a detection signal. The control unit is electrically connected to the detection circuit, and is configured to control the first through the fourth switches according to a plurality of on-off states, to receive the detection signal and a V.sub.BUS signal from the receiving end in the plurality of on-off states, to generate a plurality of detection results, and to determine the type of the USB cable according to the plurality of detection results.

A serial peripheral interface of an integrated circuit includes: a first transfer pin for receiving an instruction and an address; and a clock pin for inputting a plurality of timing pulses each having a rising edge and a falling edge. After the first transfer pin receives the instruction, the integrated circuit receives the address through the first transfer pin in continuity with the receipt of the instruction. The first transfer pin receives the instruction at either of the rising edges and the falling edges of the timing pulses and receives the address at both of the rising edges and falling edges of the timing pulses.

A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.

A power management device and microprocessor within a System-in-Package (SiP) are provided with communication signals externally available as outputs from the SiP so that they can be configured by an external device. Methods for the configuration of SiPs and Power Management Integrated Circuits (PMICs) packaged within a SiP are also provided.

A power management device and microprocessor within a System-in-Package (SiP) are provided with communication signals externally available as outputs from the SiP so that they can be configured by an external device. Methods for the configuration of SiPs and Power Management Integrated Circuits (PMICs) packaged within a SiP are also provided.

A flexible input/output (I/O) expansion card connection and communication technique are provided. The flexible I/O expansion card is, in some examples, a mezzanine expansion card that may be a single width mezzanine expansion card, a double width expansion card, or a quad width expansion card. Multiple connectors on a mainboard provide a slot to receive plug in (insertion) of an expansion card. A slot is associated with a communication bus (e.g., Peripheral Component Interconnect (PCI)) established between the expansion card and an associated processor. The expansion card (or more than one expansion card) may be inserted in multiple orientations with respect to the multiple connectors. Automatic adjustment of communication on the communication bus may be implemented via one or more hardware level and/or software assisted translations to allow the mezzanine expansion card to function in a normal or a reverse (180 degrees relative to normal) orientation.