A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

Various systems and methods for configuring a pluggable computing device are described herein. A pluggable computing device may be configured to be compatible with a pluggable host system using a default communication channel to obtain configuration settings and configure a programmable logic device on the pluggable computing device. The pluggable computing device may perform chain of trust processing on the pluggable host system. The pluggable computing device may be disposed on a compute card, which may include a heat sink in a particular configuration.

Various systems and methods for configuring a pluggable computing device are described herein. A pluggable computing device may be configured to be compatible with a pluggable host system using a default communication channel to obtain configuration settings and configure a programmable logic device on the pluggable computing device. The pluggable computing device may perform chain of trust processing on the pluggable host system. The pluggable computing device may be disposed on a compute card, which may include a heat sink in a particular configuration.

System settings for an information handling system are updated based on the operating system version of an information handling system that is installed or updated on the information handling system. An operating system template to the version of the operating system is retrieved and staged to a shared memory access/partition accessible by a basic input/output system (BIOS) of information handling system. A system policy enforcer of the BIOS accesses configuration settings from the staged corresponding operating system template and applies the accessed accessing configuration settings to the information handling system.

System settings for an information handling system are updated based on the operating system version of an information handling system that is installed or updated on the information handling system. An operating system template to the version of the operating system is retrieved and staged to a shared memory access/partition accessible by a basic input/output system (BIOS) of information handling system. A system policy enforcer of the BIOS accesses configuration settings from the staged corresponding operating system template and applies the accessed accessing configuration settings to the information handling system.

A battery cell monitoring circuit comprises an input pin; a reset command detection circuit comprising an integrator circuit coupled to the input pin; a counter circuit coupled to an output terminal of the integrator circuit; and a one-shot circuit coupled to an output terminal of the counter circuit; a logic gate coupled to an output terminal of the one-shot circuit; and a reset circuit coupled to the logic gate.

A battery cell monitoring circuit comprises an input pin; a reset command detection circuit comprising an integrator circuit coupled to the input pin; a counter circuit coupled to an output terminal of the integrator circuit; and a one-shot circuit coupled to an output terminal of the counter circuit; a logic gate coupled to an output terminal of the one-shot circuit; and a reset circuit coupled to the logic gate.

The present disclosure relates to a chip booting control method, a chip, a display panel, and an electronic apparatus. The method is applied to a control circuit of a chip, and the chip further includes a buffer. The method includes: reading first booting information from the buffer in response to a chip triggering non-power-down reset, the first booting information being used to boot the chip; determining whether the first booting information satisfies a first preset condition; and booting the chip according to the first booting information in response to the first booting information satisfying the first preset condition.

A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a validation signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the validation signal. The first starting voltage is lower than the second starting voltage.