A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

Systems, apparatus, and methods that control power consumption in a processor are disclosed. One system apparatus, and method includes a processor that operates in at least a first power control mode including a first power amount and a second power control mode including a second power amount lower than the first power amount and a power control device. The power control device is configured to control power consumption in the processor, change a power control mode of the processor to the first power control mode in response to a first excess time period in which the power consumption of the processor exceeds a first reference power for a first period of time, and change the power control mode of the processor to the second power control mode in response to a second period of time in which the power consumption is less than or equal to a second reference power.

Systems, apparatus, and methods that control power consumption in a processor are disclosed. One system apparatus, and method includes a processor that operates in at least a first power control mode including a first power amount and a second power control mode including a second power amount lower than the first power amount and a power control device. The power control device is configured to control power consumption in the processor, change a power control mode of the processor to the first power control mode in response to a first excess time period in which the power consumption of the processor exceeds a first reference power for a first period of time, and change the power control mode of the processor to the second power control mode in response to a second period of time in which the power consumption is less than or equal to a second reference power.

A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

An apparatus and method for providing efficient power management for data transfer protocols between components. A source generates requests and a destination services the requests. The source and destination support a communication protocol that includes both a transfer channel and one or more transaction channels for each type of request. The source and destination rely on a valid signal and a ready signal of the transfer channels to autonomously manage power consumption. The source and destination remove any dependencies on an external power manager and make it unnecessary to add signal extensions to the communication protocol to support power management.

According to some examples, systems and methods are provided for determining a set of power states supported by a data storage device and applying an operation to the data storage device based on whether the set of power states includes a low power state.

The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.