A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

An information processing apparatus comprises: an arithmetic unit configured to perform arithmetic operation processing using a hierarchical network; a storage unit configured to store input data inputted to the arithmetic unit and output data outputted from the arithmetic unit; a transmission unit configured to transmit to the arithmetic unit the input data stored in the storage unit; a reception unit configured to receive and store in the storage unit the output data from the arithmetic unit; and a control unit configured to, in a case where the input data cannot be transmitted from the storage unit to the arithmetic unit, control supply of an operation clock to the transmission unit based on network information that indicates a structure of the hierarchical network.

An information processing apparatus comprises: an arithmetic unit configured to perform arithmetic operation processing using a hierarchical network; a storage unit configured to store input data inputted to the arithmetic unit and output data outputted from the arithmetic unit; a transmission unit configured to transmit to the arithmetic unit the input data stored in the storage unit; a reception unit configured to receive and store in the storage unit the output data from the arithmetic unit; and a control unit configured to, in a case where the input data cannot be transmitted from the storage unit to the arithmetic unit, control supply of an operation clock to the transmission unit based on network information that indicates a structure of the hierarchical network.

An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.

A touch controller includes a touch data generator that is connected to a plurality of sensing lines, the touch data generator sensing a change in capacitance of a sensing unit connected to each of the sensing lines and generating touch data by processing the sensing signal corresponding to the result of sensing; and a signal processor that controls a timing of generating the touch data by receiving at least one piece of timing information for driving a display panel from a timing controller, and then providing either the timing information or a signal generated from the timing information as a control signal to the touch data generator.

The power consumption of a control device or a data processing system is reduced. Safety is enhanced. An electronic device is operated in a simple way. A control device includes an arithmetic circuit, an input unit, and a power management unit. The input unit includes a sensor element. The power management unit has a function of controlling supply and shutdown of power to the arithmetic circuit. The power management unit has a function of supplying power to the arithmetic circuit in response to a detection signal output from the sensor element. The sensor element includes one or more selected from an acceleration sensor, an angular velocity sensor, and a magnetic sensor. The arithmetic circuit includes a register. The register includes a first circuit and a second circuit. The register has a function of storing, in the second circuit, first data stored in the first circuit in a period during which the power management unit supplies power to the arithmetic circuit and retaining the first data, in a period during which the power management unit stops power supply to the arithmetic circuit. The arithmetic circuit has a function of generating second data with use of signal data output from the sensor element and the first data.

The power consumption of a control device or a data processing system is reduced. Safety is enhanced. An electronic device is operated in a simple way. A control device includes an arithmetic circuit, an input unit, and a power management unit. The input unit includes a sensor element. The power management unit has a function of controlling supply and shutdown of power to the arithmetic circuit. The power management unit has a function of supplying power to the arithmetic circuit in response to a detection signal output from the sensor element. The sensor element includes one or more selected from an acceleration sensor, an angular velocity sensor, and a magnetic sensor. The arithmetic circuit includes a register. The register includes a first circuit and a second circuit. The register has a function of storing, in the second circuit, first data stored in the first circuit in a period during which the power management unit supplies power to the arithmetic circuit and retaining the first data, in a period during which the power management unit stops power supply to the arithmetic circuit. The arithmetic circuit has a function of generating second data with use of signal data output from the sensor element and the first data.

A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.