A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

The application provides a processing method and device. Weights and input neurons are quantized respectively, and a weight dictionary, a weight codebook, a neuron dictionary, and a neuron codebook are determined. A computational codebook is determined according to the weight codebook and the neuron codebook. Meanwhile, according to the application, the computational codebook is determined according to two types of quantized data, and the two types of quantized data are combined, which facilitates data processing.

The disclosure relates to a baseband processing method, comprising: receiving a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section; decoding at least part of the control section to detect a DL grant information; if the DL grant information is detected, determine a number of granted data resource blocks from the DL grant information; and adjust at least one of a clock rate and supply voltage of the baseband processing based on the number of granted resource blocks.

Systems and methods of adaptive thermal control are provided for information handling system platforms that may be implemented to automate and scale fan control settings by making the fan control settings relative to a reported component thermal control parameter value from a component of an information handling system platform, such as a CPU or other heat generating component. In one example, bounds for system use of vendor or component manufacturer-reported thermal control parameter values may be set for system cooling so as to confine use of these values within information handling system platform limits characterized by a manufacturer of an information handling system platform.

Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

A computer system including a PCH (platform controller hub), a CPLD (complex programmable logic device), a first switch and a processor, and a control method are provided to control the operation frequency of the processor. The CPLD is coupled to the PCH and the first switch. The processor is coupled to the first switch. The PCH produces and outputs a second control signal according to the first firmware and a first control signal from a command input unit. The CPLD produces and outputs a third control signal according to the second firmware and the second control signal. The first switch receives the third control signal and is turned on to output a triggering signal when the third control signal is valid. The processor includes a PROCHOT pin. The processor receives the triggering signal and triggers the PROCHOT pin for frequency control.

A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.

An electronic device is provided. The electronic device includes: a display device including a plurality of light-emitting elements for displaying an optical image on a front side of the display device; an illumination element integrated into the display device and configured to emit light for illuminating a scene in front of the front side of the display device; an optical sensor configured to sense reflections of the light from the scene; an optical transmitter configured to transmit an optical control signal encoded with control information for controlling light emission by the illumination element; and an optical receiver integrated into the display device and configured to receive the optical control signal and generate an electrical control signal based on the optical control signal. The electronic device further includes a driver circuit integrated into the display device and configured to drive the illumination element based on the electrical control signal.

Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.