A data interface sleep and wakeup method includes receiving data information sent by a second electronic device, where the data information includes sleep information, and setting, based on the sleep information, at least one data interface to either a sleep state or a wakeup state.

Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

A circuit system and a method of analyzing audio or video input data that is capable of detecting, classifying, and post-processing patterns in an input data stream. The circuit system may consist of one or more digital processors, one or more configurable spiking neural network circuits, and digital logic for the selection of two-dimensional input data. The system may use the neural network circuits for detecting and classifying patterns and one or more the digital processors to perform further detailed analyses on the input data and for signaling the result of an analysis to outputs of the system.

A software switch and a method performed by the software switch are disclosed. The software switch receives, from a node deploying a virtual machine, a request for a virtual port to be polled by the virtual machine. The request includes a Central Processing Unit “CPU” identity identifying a CPU on which the virtual machine executes. The request includes an indication of a clock frequency at which the CPU is set to operate. The software switch determines a number of packets in a queue associated with the virtual port. The software switch adjusts the clock frequency of the CPU based on the number of packets in the queue. A corresponding computer program and a computer program carrier are also disclosed.

A software switch and a method performed by the software switch are disclosed. The software switch receives, from a node deploying a virtual machine, a request for a virtual port to be polled by the virtual machine. The request includes a Central Processing Unit “CPU” identity identifying a CPU on which the virtual machine executes. The request includes an indication of a clock frequency at which the CPU is set to operate. The software switch determines a number of packets in a queue associated with the virtual port. The software switch adjusts the clock frequency of the CPU based on the number of packets in the queue. A corresponding computer program and a computer program carrier are also disclosed.