As the volume of data under management expands rapidly, so do the costs associated with storing and that data on secondary storage devices. The illustrative approach provides an improvement to the information management system by delaying certain tasks that meet a set of criteria until a specified threshold is met. The system receives a request to be performed on a set of data stored on secondary devices. Power management module determines whether the task satisfies a set of criteria for delayed execution, queues the task, and when a specified threshold of the queued tasks is met powers up the necessary components to execute the tasks.

According to some examples, systems and methods are provided for determining a set of power states supported by a data storage device and applying an operation to the data storage device based on whether the set of power states includes a low power state.

A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

Systems and methods for peer data storage device messaging over a control bus for power management are disclosed. Storage devices may include a host interface configured to connect to a host system and a control bus interface to connect to a control bus. Peer data storage devices may establish peer communication through the control bus interface, determine a power state, receive a power change indicator from a peer data storage device, and initiate a change in their power state. The peer data storage devices may manage their collective power as a power pool and increase or decrease power use without host intervention.

A storage unit is disclosed. The storage unit may include an interface to a host and storage for a data. A receiver may receive from a host a boot power data. The boot power data may including a first power level and a duration. A circuit may boot the storage unit based at least in part on the boot power data. The storage unit may include a second power level, with the first power level greater than the second power level.

A data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive information from a host about which area, if any, in a host memory buffer will be powered on during a low-power state; and in response to the information indicating that a first area of the host memory buffer will be powered on during the low-power state, flush data from a second area of the host memory buffer that will not be powered on during the low-power state to the first area of the host memory buffer prior to entering the low-power state. Other embodiments are provided.

A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.

A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

An image processing apparatus includes a connection unit, a first power supply unit, a second power supply unit, and a control device. The connection unit is connected to an electronic apparatus including a controlled device and a communication relay unit. The first power supply unit can supply power to the controlled device. The second power supply unit can supply power to the communication relay unit. The control device is capable of switching a power supply state by the first power supply unit and the second power supply unit between at least a first stop state in which power supply by the first power supply unit is continued and power supply by the second power supply unit is stopped and a second stop state in which power supply by the first power supply unit and the second power supply unit is stopped.

Systems and methods, according to the present disclosure, determines a duration of the current queue of commands in the controller, executes all full commands capable of being executed prior to the beginning of a low power cycle. Commands that are not executed may be re-fetched when the device enters a power mode. In an alternate embodiment, a portion of a command that is executable prior to the beginning of a low power cycle is executed, with the un-executed portion of the command being stored on the device, in an “always on” or AON memory. This un-executed portion is fetched and executed when the device enters the power mode.