G06F11/002

MEMORY SYSTEM AND OPERATING METHOD THEREOF
20230041076 · 2023-02-09 ·

A memory device is provided to include: a plurality of memory cells; a peripheral circuit configured to perform an operation on the plurality of memory cells; a temperature circuit configured to measure a temperature of the memory device; a monitoring component configured to generate, based on whether a measured temperature is within a reference range, monitoring information representing an operation mode that is either a normal mode in which the operation is performed or a protection mode in which the operation is suspended; and an operation controller configured to output a signal for controlling the operation according to the monitoring information. The monitoring component is further configured to store the monitoring information and output the monitoring information to the operation controller in response to receiving the measured temperature from the temperature circuit.

Operating a power source as a heating device in an information handling system (IHS)
11520392 · 2022-12-06 · ·

Systems and methods for operating a power source as a heating device in an Information Handling System (IHS) are described. In some embodiments, an IHS may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive an indication to increase a temperature of the IHS and, in response to the indication, concurrently set a first power supply in source mode and a second power supply in sink mode.

METHOD, ARRANGEMENT, AND COMPUTER PROGRAM PRODUCT FOR ORGANIZING THE EXCITATION OF PROCESSING PATHS FOR TESTING A MICROELECTRIC CIRCUIT

The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.

Method for mitigating temperature of electronic device

Embodiments herein disclose a method for mitigating a temperature of an electronic device. The method includes determining, by the electronic device, the temperature of the electronic device, while a plurality of applications are executed on the electronic device, wherein each of the applications from the plurality of applications is associated with a first RAT. Further, the method includes detecting, by the electronic device, that the temperature of the electronic device meets thermal mitigation criteria. Further, the method includes mitigating, by the electronic device, the temperature of the electronic device by switching the application from the plurality of applications from the first RAT to a second RAT in response to detecting that the temperature of the electronic device meets the thermal mitigation criteria.

Data accessing method using dynamic speed adjustment with aid of thermal control unit, and associated apparatus

A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.

FILTRATION THRESHOLDING

A measurement system includes a receiver configured to receive a measurement signal indicative of a parameter of a measured object. The measurement system also includes a processor configured to iteratively filter the measurement signal using a threshold value. The processor is also configured to adjust the threshold value for each iteration of filtration and determine a signal-to-noise ratio for each iteration of filtration. The processor is also configured to set a filter threshold value to the threshold value for the iteration based on the signal-to-noise ratio.

System for modeling intelligent sensor selection and placement

The present system for modeling intelligent sensor selection and placement takes signal and sensor information and calculates a statistical inference. As signal data passes through a series of processors, it is transformed by functions to account for signal emission, sensor reception, environmental factors, and noise. This produces a simulation of what the emitted signal would appear to be at a given sensor. The system may be used to select the most effective sensors for a given area or to determine the best sensor coverage for a given area.

Integrated circuit self-repair method and integrated circuit thereof

An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.

A DATA PROCESSING METHOD

A computer-implemented data processing method to improve information quality in data sequences by attenuating noise in the data sequences, the method including: receiving input data sequences, having a plurality of elements, from one or more sensors, each of the elements having at least one dimensional component; performing a spectral analysis on the dimensional component of each of the elements, independently, to estimate a signal profile of the input data sequences; estimating a noise profile of the input data sequences using calibration data associated with the sensor; dynamically calculating a time-constant for a noise attenuation filter, and adapting the time-constant over time, for each one of the elements in the input data sequences, based on the relationship between the noise profile and the signal profile; applying the noise attenuation filter for each one of the elements to each one of the elements, respectively, to filter the input data sequences to derive filtered data sequences; and outputting the filtered data sequences.

INTEGRATED CIRCUIT SELF-REPAIR METHOD AND INTEGRATED CIRCUIT THEREOF
20220026489 · 2022-01-27 · ·

An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.