An apparatus comprises a memory having a data cache stored therein and a control circuit operably coupled thereto. The control circuit is configured to update that data cache in accordance with a scheduled update time. In the latter regards, by one approach, the control circuit computes selected entries for the data cache prior to the scheduled update time pursuant to a prioritization scheme to provide a substitute data cache. At the scheduled update time, the control circuit switches the substitute data cache for the data cache such that data queries made subsequent to the scheduled update time access the substitute data cache and not the data cache.

In one embodiment, a method for margin determination for a computing system with a real time operating system and priority preemptive scheduling comprises: scheduling a set of tasks to be executed in one or more partitions, wherein each is assigned a priority, wherein the tasks comprise periodic and/or aperiodic tasks; executing the set of tasks on the computing system within the scheduled periodic time window; introducing an overhead task executed for an execution duration controlled either by the real time operating system or by the overhead task; controlling the overhead task to converge on a point of failure at which a length of the execution duration of the overhead task causes either: 1) a periodic task to fail to execute within a deadline, or 2) time available for the aperiodic tasks to execute to fall below a threshold; and defining a partition margin corresponding to the point of failure.

A firmware protection module implements a hybrid firmware protection scheme on a computing device. The firmware protection module intercepts a message from a processor to a memory of the computing device. The message includes a command and an address in the memory corresponding to a firmware module stored in the module. The firmware protection module determines whether the command in the message is prohibited and whether the address in the message is protected. Responsive to a determination that the command is prohibited and the address is protected, the firmware protection module prevents at least a portion of the message from reaching the memory.

A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.

Implementations include providing, by a computer-executed migration advisor executing within a run-time of a source database system, a query data set including queries processed by the source database system during production use of the source database system, providing, by the migration advisor, an object data set including data representative of database objects stored within a database of the source database system, generating, by the migration advisor, a list of query-level features and a list of object-level features, each feature in the list of query-level features and each feature in the list of object-level features including a feature that is deprecated in a target database system, resolving one or more issues represented by features of one or more of the list of query-level features and the list of object-level features, and executing migration of the database of the source database system to the database of the target database system.

The subject technology selects a most recently created file from a set of files stored in a source table. The subject technology iterates, in the source table, starting from the most recently created file up to an age threshold to select a first set of files for performing a first defragmentation process. The subject technology sets an indication corresponding to a particular file that is a last file, from the first set of files, that meets the age threshold. The subject technology performs the first defragmentation process on the selected first set of files. The subject technology determines that the first defragmentation process was successful.

It is provided an information processing apparatus. The information processing apparatus includes memory, a processor configured to control a device, a circuit connected with the memory, the processor and the device and configured to store a first sequence which causes a failure of the device in a first storage area in the memory, store a second sequence which prevents the failure in a second storage area in the memory, determine whether a third sequence for controlling the device included in a packet output from the processor is the first sequence, coordinate the third sequence by using the second sequence when the third sequence is the first sequence, and generate a packet including the coordinated third sequence.

A dynamic vision sensor (DVS) or change detection sensor reacts to changes in light intensity and in this way monitors how a scene changes. This disclosure covers both single pixel and array architectures. The DVS may contain one pixel or 2-dimensional or 1-dimensional array of pixels. The change of intensities registered by pixels are compared, and pixel addresses where the change is positive or negative are recorded and processed. Analyzing frames based on just three values for pixels, increase, decrease or unchanged, the proposed DVS can process visual information much faster than traditional computer vision systems, which correlate multi-bit color or gray level pixel values between successive frames.

An image processing apparatus includes a processing section and a control section configured to instruct operation of the processing section. The control section executes, before sending, to the processing section, a first instruction corresponding to an instruction that caused an error in the past, an error avoidance operation based on instruction history information and operation state history information acquired from a storing section that stores the instruction history information and the operation state history information, the instruction history information indicating an instruction given to the processing section by the control section, the operation state history information indicating an operation state of the processing section caused by the instruction.

Embodiments of the invention are directed to systems, method, and devices for detecting failures in distributed systems. A failure detection platform may identify anomalies in time series data, the time series data corresponding to historical network messages. The anomalies can be labeled and used to train a first predictive model. At least one other model may be trained using the time series data, the anomaly labels and a supervised machine-learning algorithm. A third model can be trained to identify a system failure based at least in part on the outputs provided by the first and the second model. The third model, once trained, can be utilized to predict a future system failure.