G06F11/0763

Vehicular control apparatus
11580223 · 2023-02-14 · ·

A vehicular control apparatus is used in an onboard system provided with a plurality of information processors mutually connected via a communication bus, and includes a storage section for storing information, and an arithmetic section for executing a process based on the information stored in the storage section. The information contains first management information relating to a security abnormality as a communication data abnormality owing to security attack from outside the onboard system, and second management information relating to a safety abnormality as a communication data abnormality owing to an abnormality in the onboard system. The first management information contains first limit condition information indicating a first limit condition for executing a security coping with the security abnormality. The second management information contains second limit condition information indicating a second limit condition for executing a safety coping with the safety abnormality. Upon detection of the communication data abnormality in the onboard system, the arithmetic section determines a coping content to the detected communication data abnormality based on the first management information and the second management information.

Information processing apparatus and information processing method

An information processing device includes: an identifier adding unit that adds identifiers including at least one type of valid identifier to each of a plurality of pieces of information; a plurality of input memories that hold the plurality of pieces of information and the identifiers, respectively; a plurality of output memories that hold a plurality of pieces of information processed by the processing unit and the identifiers added to the plurality of pieces of information, respectively; and an identifier inspecting and verifying unit that performs inspection and verification by comparing at least one identifier that becomes an inspecting and verifying target identifier among the identifiers to the valid identifier held in the input memory corresponding to the output memory that holds the inspecting and verifying target identifier.

Firmware descriptor resiliency mechanism

An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

SAFEGUARDING A SYSTEM AGAINST FALSE NEGATIVES

A computer-implemented method for safeguarding a system against false negatives. The method includes: receiving a time series of a criticality, the system including a functionality that is triggered when the criticality meets a first predetermined criterion; computing a time series of a reference, the reference being a comparison criticality for triggering the functionality; computing a time series of an error measure based on the time series of the criticality and the time series of the reference, a non-triggering of the functionality being classified as a false negative when a portion of the time series of the error measure meets a second predetermined criterion; and identifying at least one near-false negative, a non-triggering of the functionality of the system being classified as a near-false negative when a portion of the time series of the error measure meets a third predetermined criterion, but not the second predetermined criterion.

HARDWARE-BASED SENSOR ANALYSIS
20230229549 · 2023-07-20 ·

A method of monitoring messages from a sensor using an integrated circuit is provided. The messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit. The interconnect circuitry connects the sensor to one or more core devices configured to process the messages. A first hash value is calculated for the first message. The first hash value is compared to one or more prior hash values stored in a hash store. Each prior hash value of the one or more prior hash values corresponds to a message that was read from the interconnect circuitry prior to the first message. A corrective action is performed when a difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold.

Error recovery in digital communications
11700317 · 2023-07-11 · ·

Electronic communications between a client device and a server device are improved by providing a middleware component that incorporates electronic data read and/or written to a database in a hybrid data structure. The hybrid structure is further designed to allow for “NULL” or other pre-defined data values when one or more data fields are unavailable or erroneous. The client device, in turn, can be configured to check for the pre-defined data values in certain fields and to gracefully process such values. The hybrid structure with pre-defined error values therefore provides for very efficient data transmittal and processing, while retaining the ability to handle errors or other unusual situations relating to the data.

Cross-component health monitoring and improved repair for self-healing platforms
11544129 · 2023-01-03 · ·

Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.

ORDERED DATA SUB-COMPONENT EXTRACTION
20220398145 · 2022-12-15 ·

Apparatuses and methods for extracting ordered data sub-components from a data item are disclosed. A received data item has a data structure to accommodate multiple data sub-components. The data item indicates which data sub-components are valid. Adders sum respective subsets of indications of the valid data sub-component positions, with each adder covering one more position than the previous adder. Transitions of the counts generated by the respective adders are used to determine the ordinal valid data sub-component positions in the data item, which can then be output on the basis of the data item and the identified transition positions. Without requiring feedback paths from an identified earlier ordinal position to identify a later ordinal position, the set of ordered data sub-components can be extracted more quickly.

History management method, history management apparatus and history management system
11513916 · 2022-11-29 · ·

A history management method for managing history information of multiple vehicles using blockchains is provided. The history management method includes generating a master block from history information collected in a vehicle, setting a node serving as a storage destination of a backup block of the master block per block, storing, together with the master block, backup blocks that are different in history information collecting vehicle from the master block in a block storage unit, and sending the backup block for a particular vehicle requested in a recovery request.

Secure memory translations
11507514 · 2022-11-22 · ·

An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.