A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.

A rework re-timer with forward error correction handling is disclosed. An example first intermediate transceiver includes a first interface to communicatively couple the first intermediate transceiver with a first computing device, a second interface to communicatively couple the first intermediate transceiver to a second intermediate transceiver configured to be communicatively coupled with a second computing device, an auto-negotiation controller to: terminate a first auto-negotiation with the first computing device before the first auto-negotiation is completed, transmit, to the second transceiver, first capabilities of the first computing device determined during the first auto-negotiation, and perform a second auto-negotiation with the first computing device utilizing the first capabilities of the first computing device and second capabilities of the second computing device received from the second transceiver.

The embodiments of the present application provide a polar code construction method and apparatus, which relate to the field of communications technology. The method comprises: obtaining a polar weight spectrum for each polarized channel; calculating an upper bound of error probability of each polarized channel based on the obtained polar weight spectrum, distribution probability density of a fading factor of a fading channel, and a signal-to-noise ratio of the fading channel; taking a logarithm of the calculated upper bound of the error probability for each polarized channel and obtaining a reliability metric of the polarized channel based on the taken logarithm, wherein the smaller the metric value is, the higher the reliability of the polarized channel is; sorting all polarized channels in an ascending order of the reliability metric and selecting part of the polarized channels having a lowest reliability metric for transmitting information bits and the remaining polarized channels for transmitting frozen bits. According to the embodiments of the present application, performing polar code construction under the condition of a fading channel can improve the efficiency of polar code construction.

A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

There is provided a processing device to which different unique constants are allocated among devices of the same type, the processing device comprising: a processing unit that performs a calculation based on a common code that is issued by a code issuing device and is used in common by the plurality of processing devices, and the specific constant allocated to the processing device, and executes a subsequent process using a result of the calculation, wherein, prior to the subsequent process, the processing unit executes a determination of whether or not each of a result of a calculation based on the specific constant allocated to the processing device and a result of a calculation based on the specific constant allocated to at least one other processing device is a valid value.

A computer program product, a device, a functionally secure programmable controller and a method for processing data via coded operations in a number of cycles, wherein an uncoded variable x is coded with a cycle-specific signature D and a variable-specific signature B.sub.x to form a coded variable x.sub.c in accordance with the relationship: x.sub.c=D.Math.x+B.sub.x.

A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

A magnetic tape device or system can store erasure encoded data that generates a multi-dimensional erasure code corresponding to an erasure encoded object comprising a code-word (CW). The multi-dimensional erasure code enables using a single magnetic tape in response to a random object/file request, and correct for an error within the single magnetic tape without using other tapes. Encoding logic can further utilize other magnetic tapes to generate additional parity tapes that recover data from an error of the single magnetic tape in response to the error satisfying a threshold severity for a reconstruction of the erasure coded object or chunk(s) of the CW. The encoding logic can be controlled, at least in part, by one or more iterative coding processes between multiple erasure code dimensions that are orthogonal to one another.

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an i.sup.th operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the i.sup.th operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.