An application executed on a device reads a portion of a memory during one of an initialization operation and a regular read operation. The application may trigger a preventative read operation during at least one regular read operation. During the preventative read operation the application selects at least one block and at least one page for the preventative read operation. The application determines a cadence for the preventative read operation. The application obtains an error correction code (ECC) status for the portion of the memory, determines if a number of errors associated with the portion is greater than a predefined ECC threshold and performs a correction, responsive to determining that a number of errors associated with the portion is greater than a predefined ECC threshold.

A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.

Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

A controller for controlling a memory device may include: an end-to-end decoder suitable for correcting an error in the unit user data and the corresponding end-to-end parity; an internal encoder suitable for generating a data chunk by adding a first internal parity to the source word which includes the unit user data and the end-to-end parity from the end-to-end decoder and buffering the source word into a buffer; an integrity checker suitable for determining whether an error is included in the source word, by using the end-to-end parity from the end-to-end decoder; and a parallel parity generator suitable for receiving the source word from the buffer according to a result of the determination, and completing a parallel parity based on a predetermined number of source words received, wherein the internal encoder is further suitable for generating a parity chunk by adding a second internal parity to the completed parallel parity.

In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

Methods, systems, and devices for compressed logical-to-physical mapping for a memory bypass for error detection and correction are described. A memory device may include error detection and correction circuitry for detecting and correcting errors in data that is read from a memory array of the memory device. To reduce read latencies, the memory device may include bypass circuitry that enables it to transmit the data to the host device before or during error detection. If the memory device determines that the data is erroneous, the memory device may transmit an alert to the host device concurrently with or after transmitting the data. The memory device may perform error correction on the data and store corrected data in a register. Based on receiving an alert, the host device may issue one or more additional read commands to re-read the data from the memory bank or read the corrected data from the register.