A data processing system may include a memory module; and a controller configured to exchange data with the memory module in response to a request received from a host. The controller divide a first data into a first data group to error correction and a second data group not to error correction in response to the first data and a first data write request received from the host, generates a first meta data for error correction for the first data group, configures a first data chunk that includes the first data and the first meta data, and transmits the first data chunk to the memory module.

A controller for controlling a memory device may include: an end-to-end decoder suitable for correcting an error in the unit user data and the corresponding end-to-end parity; an internal encoder suitable for generating a data chunk by adding a first internal parity to the source word which includes the unit user data and the end-to-end parity from the end-to-end decoder and buffering the source word into a buffer; an integrity checker suitable for determining whether an error is included in the source word, by using the end-to-end parity from the end-to-end decoder; and a parallel parity generator suitable for receiving the source word from the buffer according to a result of the determination, and completing a parallel parity based on a predetermined number of source words received, wherein the internal encoder is further suitable for generating a parity chunk by adding a second internal parity to the completed parallel parity.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may disable ECC functions of the memory devices. When the ECC function is disabled by the host device, the memory device may deactivate various ECC periphery components coupled with an ECC circuit of the memory device to reduce power consumption of the memory device. In some cases, the memory device may disconnect an electrical power supply to the ECC periphery components. In other cases, the memory device may selectively disable the ECC periphery components or block an access command from reaching the ECC periphery components during an access operation. Further, the ECC array may be configured to replace faulty portions of a main array of the memory device when the ECC function is disabled.

A controller sets the processing in accordance with an error that may occur in data. A controller for controlling a machine or a facility includes a storage unit, a diagnosis unit that diagnoses the presence of an error in data written in a memory space of the storage unit or data read from the memory space, and a processing unit that performs processing in accordance with a diagnosis result obtained by the diagnosis unit. The processing unit performs appropriate processing when an error is detected in data within a set range of the memory space in which the diagnosis unit is to be enabled.

Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.