Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

A system includes a memory device storing groups of managed units and a processing device operatively coupled to the memory device. The processing device is to, during power on of the memory device, perform including: causing a read operation to be performed at a subset of a group of managed units; determining a bit error rate related to data read from the subset of the group of managed units; and in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.

Methods, systems, and devices for techniques for memory error correction are described. A memory device may operate cycles associated with refresh operations and cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device may include an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first, the memory device may modify the error correction counter and maintain the refresh counter. Alternatively, in response to receiving a command of a second, the memory device may modify the refresh counter and maintain the error correction counter.

Methods, systems, and devices for techniques for memory error correction are described. A memory system may support a refresh with error correction code (ECC) operation. The refresh with ECC operation may be indicated in a command from a host device to a memory device, or the memory device may support executing the refresh with ECC operation autonomously, for example as part of a self-refresh operation. The refresh with ECC operation may cause the memory system to, as part of a refresh operation for a row of a memory array, perform an error correction operation on at least a portion of the row. The error correction operation may correct bit errors in a set of data before an additional bit of the set of data is corrupted. The address of the portion of the row may be determined using one or more counters associated with an ECC patrol block.

A system-on-chip (SoC) can include a processor, a network controller configured to provide a network interface, and a memory controller configured to perform memory scrubbing. A memory patrol driver executing on the processor can initiate direct memory access (DMA) transfers to read successive portions of the memory by configuring corresponding DMA descriptors at a certain time interval. The network controller can perform each DMA transfer to read a corresponding portion of the memory, which can cause the memory controller to scrub the corresponding portion of the memory. The scrubbed data is sent to the network controller, which is discarded by the network controller.

A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.

A semiconductor chip with error detection and correction includes multiple pipes and each pipe is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipes to generate a number of events consisting of read- and/or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can centrally detect and correct erroneous memory entries across the plurality of storage elements.

A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. One or more of the computing devices and/or the storage devices may be used to rebuild data that may be lost due to a power failure.

A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).