A method of performing fault detection during computations relating to a neural network comprising a first neural network layer and a second neural network layer in a data processing system, the method comprising: scheduling computations onto data processing resources for the execution of the first neural network layer and the second neural network layer, wherein the scheduling includes: for a given one of the first neural network layer and the second neural network layer, scheduling a respective given one of a first computation and a second computation as a non-duplicated computation, in which the given computation is at least initially scheduled to be performed only once during the execution of the given neural network layer; and for the other of the first and second neural network layers, scheduling the respective other of the first and second computations as a duplicated computation.

A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.

A first processing element is configured to execute a first thread and one or more second processing elements are configured to execute one or more second threads that are redundant to the first thread. The first thread and the one or more second threads are to selectively bypass one or more comparisons of results of operations performed by the first thread and the one or more second threads depending on whether an event trigger for the comparison has occurred a configurable number of times since a previous comparison of previously encoded values of the results. In some cases the comparison can be performed based on hashed (or encoded) values of the results of a current operation and one or more previous operations.

A data processing device provided with an error detection unit includes a processor arranged to support execution of an operation including a first sequence of instructions and execution of a second sequence of instructions implementing the operation, the first and second sequences of instructions generating, when in use, a first result and a second result, respectively. Configurable circuitry is also provided and arranged to support a repository to receive the first result and the second result following generation thereof. The configurable circuitry is configured as a function comparator unit arranged to compare the first and second results for consistency and to control further execution of the first implementation and the second implementation in response to a result of the comparison.

A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.

An information processing apparatus includes a thread scheduler that allocates a process to multiple process execution hardware that process a program having a graph structure. The information processing apparatus includes: a code reader that reads a diagnostic code stored in advance; and an allocator that causes the multiple process execution hardware to execute the diagnostic code so as to complete diagnosis within a mean time to failure.

An information processing apparatus includes a thread scheduler that allocates a process to multiple process execution hardware that process a program having a graph structure. The information processing apparatus includes: a code reader that reads a diagnostic code stored in advance; and an allocator that causes the multiple process execution hardware to execute the diagnostic code so as to complete diagnosis within a mean time to failure.

A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.