Different cores of a multicore processor are used to provide diagnostics of sophisticated hardware without full redundancy by static assignment of the cores during individual cycles of the control program and comparison of the outputs. A method of automatically generating diverse programs for execution by these cores may modify one program to compile two different instructions without functionally changing that program through the use of DeMorgan equivalents and diverse compiler optimizations.

A simplex Flight Control Computer (FCC), usable in conjunction with a neighboring FCC, includes an input providing module for receiving sensor, system and neighboring FCC data; a processing unit for executing a command partition and a monitor partition, the processing unit receives the sensor, system data and neighboring FCC data; the monitor partition monitors the neighboring FCC data and provides a monitoring indicative signal to the neighboring FCC, and the command partition generates command signals; a hardware monitoring module provides a validity signal indicating FCC health; an output cutoff module receiving the FCC validity signal and enable signals generated by each monitor partition; the output cutoff module providing an enable signal based on a predetermined enabling strategy; and an enable switch connected with the output cutoff module and the processing unit and providing a received signal from the command partition according to the enable signal.

A computer system installed on board a carrier, communicating in a network with a data concentrator and with a monitor, and implementing at least one service that is critical for the operating safety of the carrier, the critical service being redundant in at least two instances (δ.sub.1, . . . δ.sub.m) on different respective computers (C.sub.1, . . . , C.sub.m) connected to the network, each computer (C.sub.k) implementing at least one software task implementing an instance (δ.sub.k) of the critical service being configured to implement the critical service by way of time control.

Disclosed embodiments relate to adjusting vehicle Electronic Control Unit (ECU) software versions. Operations may include receiving a prompt to adjust an ECU of a vehicle from executing a first version of ECU software to a second version of ECU software; configuring, in response to the prompt and based on a delta file corresponding to the second version of ECU software, the second version of ECU software on the ECU in the vehicle for execution; and configuring, in response to the prompt, the first version of ECU software on the ECU in the vehicle to become non-executable.

A method for controlling and/or monitoring a machine arrangement having at least one machine, in particular at least one robot, with the aid of a processor arrangement having a plurality of processors each with at least one core. The method includes selecting, in particular temporarily selecting, a first available and at least one further available core on the proviso that these cores are implemented, in particular arranged, on different processors of the processor arrangement, in particular during operation of the machine arrangement and/or on the basis of an updated directory and/or on the basis, in particular as a result, of an ascertained need for redundant processing of process signals; processing process signals redundantly with the aid of these selected cores; and controlling and/or monitoring the machine arrangement on the basis of this processing.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.

A method of performing fault detection during computations relating to a neural network comprising a first neural network layer and a second neural network layer in a data processing system, the method comprising: scheduling computations onto data processing resources for the execution of the first neural network layer and the second neural network layer, wherein the scheduling includes: for a given one of the first neural network layer and the second neural network layer, scheduling a respective given one of a first computation and a second computation as a non-duplicated computation, in which the given computation is at least initially scheduled to be performed only once during the execution of the given neural network layer; and for the other of the first and second neural network layers, scheduling the respective other of the first and second computations as a duplicated computation.

The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

An electronic apparatus is provided. The electronic apparatus includes a storage storing error-related information of an external electronic apparatus, and a processor configured to obtain first error-related information with respect to a target time interval and second error-related information with respect to a standard time interval including the target time interval and time intervals other than the target time interval, from the storage, obtain frequency information for each number of error occurrences with respect to the target time interval based on the first error-related information and frequency information for each number of error occurrences with respect to the standard time interval based on the second error-related information, and compare the frequency information for each number of error occurrences with respect to the target time interval with the frequency information for each number of error occurrences with respect to the standard time interval to identify an error occurrence level with respect to the target time interval.