A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

A system and method for partitioned snapshot creation of caches in a distributed data grid is provided. The system and method enables a snapshot to be created in a running system without quiescing a cache service. Moreover for each particular partition, execution of read/write requests are not blocked during the period that a snapshot creation task is being performed for the particular partition. The cache service thread continues to execute read requests for all partitions with write requests for the partition under snapshot experiencing delayed response. The system and method reduces the period of time for which partitions are unavailable during a snapshot process and increases the availability of cache services provided by a distributed data grid compared to prior snapshot systems.

Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

Generating datasets using approximate baselines including receiving, by a source storage system, an instruction to create, on a target storage system, a current snapshot for a source dataset stored on the source storage system, wherein no snapshots for the source dataset exist on the target storage system; selecting, as a baseline dataset, a similar dataset from a plurality of datasets on the source storage system with an existing snapshot on the target storage system, wherein the similar dataset comprises at least a portion of the source dataset; instructing the target storage system to generate a baseline snapshot for the source dataset using a copy of the existing snapshot of the baseline dataset; and transferring, from the source storage system to the target storage system, only a difference between the baseline dataset and the source dataset.

A storage system includes a CPU, a first memory module, a second memory module, and a storage device. The processor and the first memory module are installed in the same node. The second memory module are replaceable without shutting down power supply of the node. The first memory module stores an operating system and a program for managing user data to be stored in the storage device. The second memory module stores cache data of the user data to be stored in the storage device. The processor is configured to store a copy of data to be stored in the second memory module in the third memory module.

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

A memory anomaly processing method and system, an electronic device, and a storage medium. The method includes: reading a memory error quantity of a target memory bank from a memory error register; when the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank; calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter. It can be seen that, according to the present application, the memory read/write error rate may be reduced.

A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.