Patent classifications
G06F11/1666
Intelligent post-packaging repair
Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
MANAGING SETS OF TRANSACTIONS FOR REPLICATION
Methods and systems for managing sets of transactions for replication are provided. A system includes a number of origination nodes forming a source array. A sequence number generator generates sequence numbers based, at least in part, on a time interval during which a transaction is received. A subset manager groups transactions into subsets based, at least in part, on the sequence number.
INFORMATION PROCESSING SYSTEM
According to an embodiment, when a storage status of a first storage unit is recognized as a protected state, a control unit writes data to a second storage unit. When a read target address is recorded in a data migration log area, the control unit reads data from the second storage unit. When the read target address is not recorded in the data migration log area, the control unit reads data from the first storage unit.
Method for a reliability, availability, and serviceability-conscious huge page support
A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.
COLLISION HANDLING DURING AN ASYNCHRONOUS REPLICATION
Methods and systems for collision handling during an asynchronous replication are provided. A system includes a cache memory system comprising a number of cache memory pages. A collision detector detects when a host is attempting to overwrite a cache memory page that has not been completely replicated. A revision page tagger copies the cache memory page to a free page and tags the copied page as protected.
INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
An information processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to: generate first information including configuration information and/or interface information of a first program of an old version based on code of the first program of the old version, and generate second information including configuration information and/or interface information of the first program of a new version based on code of the first program of the new version; and generate information on compatibility between the first program of the old version and the first program of the new version based on whether there is a difference between the first information and the second information generated by the processor.
Redundant memory access for rows or columns containing faulty memory cells in analog neural memory in deep learning artificial neural network
Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
Regression-based calibration and scanning of data units
Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.
Modifying storage of encoded data slices based on changing storage parameters
A method includes determining a change to storage parameters associated with storage of data objects in a storage network, where a data segment of the data objects is dispersed storage error encoded into a set of encoded data slices based on dispersed storage error encoding parameters, and where the set of encoded data slices is stored in the set of storage units. The method also includes determining a storage modification process for the set of encoded data slices based on the change to the storage parameters. The method also includes executing the storage modification process such that the set of encoded data slices are stored in the storage network in accordance with the changed storage parameters.
Efficient and selective sparing of bits in memory systems
A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.