A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

As a function equivalent to a first check point restart (CPR) section (CPR function) of a mainframe system, a second CPR section is implemented in an open system. When the mainframe system executes each of job steps that form a job to be migrated from the mainframe system to the open system, the first CPR section outputs a job journal, and when the open system executes the job step migrated from the mainframe system, the second CPR section outputs a job journal, followed by comparison between the outputted job journals.

The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.

Method for operating a redundant automation system to control a technical process, wherein a second fail-safe subsystem is operated redundantly in relation to a first fail-safe subsystem, and wherein the faulty second fail-safe subsystem is used, where synchronization data is initially buffered in the second subsystem, and in the event that no errors are identified, the first fail-safe subsystem sends an error-free message to the second fail-safe subsystem to acknowledge the error-free message with an error free acknowledgment and process the initially buffered synchronization data.

A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

A method synchronizes the operation of a plurality of multicore processors. A first and a second multicore processor each have a main processor core and at least one secondary processor core that is used for executing utility programs. Only the main processor cores of the various multicore processors synchronize to one another. The at least one secondary processor core is controlled by the respective main processor core in each multicore processor. The utility programs are processed by the at least one secondary processor core and outputs are generated that are made available to the respective main processor core of the same multicore processor. Outputs from the multiplicity of multicore processors are then output in sync by the respective main processor core.

Method for operating a redundant automation system to control a technical process, wherein a second fail-safe subsystem is operated redundantly in relation to a first fail-safe subsystem, and wherein the faulty second fail-safe subsystem is used, where synchronization data is initially buffered in the second subsystem, and in the event that no errors are identified, the first fail-safe subsystem sends an error-free message to the second fail-safe subsystem to acknowledge the error-free message with an error free acknowledgment and process the initially buffered synchronization data.

A system, method, and computer readable medium for consistent and transparent replication of multi process multi threaded applications. The computer readable medium includes computer-executable instructions for execution by a processing system. Primary applications runs on primary hosts and one or more replicated instances of each primary application run on one or more backup hosts. Replica consistency between primary application and its replicas is provided by imposing the execution ordering of the primary on all its replicas. The execution ordering on a primary is captured by intercepting calls to the operating system and libraries, sending replication messages to its replicas, and using interception on the replicas to enforce said captured primary execution order. Replication consistency is provided without requiring modifications to the application, operating system or libraries.