A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.

A computer system installed on board a carrier, communicating in a network with a data concentrator and with a monitor, and implementing at least one service that is critical for the operating safety of the carrier, the critical service being redundant in at least two instances (δ.sub.1, . . . δ.sub.m) on different respective computers (C.sub.1, . . . , C.sub.m) connected to the network, each computer (C.sub.k) implementing at least one software task implementing an instance (δ.sub.k) of the critical service being configured to implement the critical service by way of time control.

Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

The method includes creating and sending a change request for a change to the system configuration of the hardware system by means of a first hardware component of the plurality of hardware components, receiving the change request by means of the further hardware components of the plurality of hardware components, checking the change request by means of the further hardware components for compatibility of the change request with the configuration of the particular receiving hardware component by using configuration data of the receiving hardware component, in the case that the requested change to the system configuration is compatible with the configuration of the receiving hardware component, generating and sending an approval of the change to the system configuration by means of the receiving hardware component, and in the case that an approval quorum of the hardware components that is necessary for consent is achieved, entering the requested change to the system configuration of the hardware system into the block chain, implementing the requested change to the system configuration in the hardware system.

A parallel processing system includes at least three parallel processors, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

A system for executing functionally equivalent applications. The system includes a cloud system including a plurality of cloud instances, the plurality of cloud instances being set up in each case to execute a functionally equivalent application in each case based on the same input data, the respective execution including a processing of the input data by the respective application in order to output an application result in each case, and a comparison device, which is set up to compare the respective application results in order to ascertain a comparison result and to output the comparison result that has been ascertained. A method for executing functionally equivalent applications, a computer program, and a machine-readable storage medium, are also described.

An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.

A fault tolerant consensus generation and communication system and method is described. Each processing node in the system receives a plurality of measurements from a sensor, calculates a consolidated value for the received plurality of measurements, transmits the consolidated value to other processing nodes, receives consolidated values from the other processing nodes, calculates a consensus value based on the calculated consolidated value and the received one or more consolidated values, transmits the calculated consensus value to the other processing nodes, receives consensus values from the other processing nodes, generates a consensus message based on the calculated consensus value, the received one or more consensus values, and a predefined criterion, and, in a case where the consensus message is not present in a consensus queue, adds the consensus message to the consensus queue.

A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.