Systems and methods take into account the criticality of workloads, the warranty needs of workloads, the warranty available time, and the lifetime of a workload to provide an optimal solution that ensures servers are used to highest extent. The warranty health of servers is computed and categorized as critical, warning, or healthy based on the number of days remaining in warranty. Workloads are tagged as short-term or long-term workloads. Workloads are also classified based on criticality. The quarantine mode for proactive high availability of servers is divided into multiple modes, including a long-time, critical-workload quarantine mode, a critical-workload quarantine mode, and a standard quarantine mode. Servers that are in quarantine mode are assigned new workloads based upon the warranty health, workload term, and workload criticality.

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

The present invention relates to a computation cell and a self-healing, fault-tolerant FPGA architecture and, more particularly, to a computation cell and an FPGA including the same, which can detect a transient internal error or permanent internal error by inputting an original function and a spare function and comparing a prestored error detection code with a generated error detection code signal. The computation cell and the self-healing, fault-tolerant FPGA architecture of the present invention can reconfigure stem cells and look-up tables included in the computation cell and can output a normal output signal even if a transient error or a permanent error is generated in an computation cell such that the corresponding computation cell and an computation tile can be normally operated.

A reconfiguration circuit (352) generates a control value for controlling an output value of a control target device based on an input value, and when a fault occurs in an information processing circuit (200) that outputs the control value generated to the control target device, performs preparation for substituting for the information processing circuit (200). Upon completion of the preparation, a reconfiguration target circuit (510) generates an output plan of a control value such that a difference between an actual output value of the control target device and an output value in a scheduled temporal transition gradually decreases, based on the scheduled temporal transition that is a temporal transition of an output value of the control target device, which is scheduled before occurrence of the fault in the information processing circuit (200), a difference between an actual output value of the control target device upon completion of the preparation and an output value in the scheduled temporal transition, and an input value and a control value before occurrence of the fault in the information processing circuit (200), and outputs a control value to the control target device instead of the information processing circuit (200) according to the output plan generated.

Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.