A test and measurement system has a test and measurement instrument, a test automation platform, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive a waveform created by operation of a device under test, generate one or more tensor arrays, apply machine learning to a first tensor array of the one or more tensor arrays to produce equalizer tap values, apply machine learning to a second tensor array of the one of the one or more tensor arrays to produce predicted tuning parameters for the device under test, use the equalizer tap values to produce a Transmitter and Dispersion Eye Closure Quaternary (TDECQ) value, and provide the TDECQ value and the predicted tuning parameters to the test automation platform. A method of testing devices under test includes receiving a waveform created by operation of a device under test, generating one or more tensor arrays, applying machine learning to a first tensor array of the one or more tensor arrays to produce equalizer tap values, applying machine learning to a second tensor array of the one or more tensor arrays to produce predicted tuning parameters for the device under test, using the equalizer tap values to produce a Transmitter Dispersion Eye Closure Quaternary (TDECQ) value, and providing the TDECQ value and the predicted tuning parameters to a test automation platform.

An operation verifying apparatus of a first embodiment acquires a log indicating the content of a sequence of operations performed on a predetermined device, identifies corresponding functions from the log, and automatically generates a program based on the identified functions. Input data, which is to serve as an argument of each of these functions, is set. Execution sets as well as test scenarios are each structured by combining a program and input data. Then each execution set is continuously executed. As a result, an operation test using a test program is executed.

A memory test method, a memory test apparatus, a device and a storage medium are provided. The memory test method includes: obtaining a central processing unit (CPU) accessible space of a memory to-be-tested; obtaining a graphics processing unit (GPU) accessible space of the memory to-be-tested; and driving a CPU to run a test program based on the accessible space of the CPU, to access the memory to-be-tested through a bus of memory to-be-tested, when the CPU runs the test program, the CPU controls a GPU to access the memory to-be-tested based on the accessible space of the GPU through the bus of memory to-be-tested.

Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

Provided are a method and an apparatus for testing AI chip computing performance, and a non-transitory computer-readable storage medium. The method includes: forming computing performance result data of a to-be-tested AI chip according to a plurality of items of simulation data formed in a development process of the to-be-tested AI chip; acquiring a function instruction set matched with a to-be-tested service function, wherein the function instruction set is composed of a plurality of instructions in a standard instruction set matched with the to-be-tested AI chip; and predicting computing time required by the to-be-tested AI chip to execute the to-be-tested service function according to the function instruction set and the computing performance result data.

A system for configuring an information handling system into a minimum configuration mode. If an information handling system hangs, embodiments may communicate with a remote access controller to set a configuration flag corresponding to a minimum configuration mode. When the information handling system starts a POST process, the BIOS checks the configuration flag. If the flag is set, the BIOS initializes a single DIMM and bypasses any PCIe slot driver initializations and any non-essential services to allow the information handling system to complete the boot process. The information handling system may boot to a UEFI code to allow a user to diagnose a problem or boot to a BIOS setup code to allow the user to enable additional DIMMs, PCIe slots and turn on non-essential services.

A method of testing a distribution center bus system having one or more of the following features: (a) opening a reserve bus breaker between a reserve bus UPS and a reserve bus, (b) initiating a self-test mode at the reserve bus UPS, (c) routing current through the reserve bus UPS, the reserve bus, a reserve bus static bypass circuit back to the reserve bus UPS, (d) testing the reserve bus to detect heat, determine any significant current loss, or identify other attributes suggesting failure, (e) identifying if a primary bus static transfer switch has tripped over to the reserve bus, and (f) terminating the self-test at the reserve bus UPS if the primary bus static transfer switch has tripped.

Devices, systems, and methods for providing an engine control system configured with a two-part test equipment monitor where at least one part is selectively removable are disclosed. An engine control system for an aircraft includes an electronic control unit (ECU). The ECU is configured to implement a production support equipment module and a selectively removable test support equipment module. The production support equipment module enables restricted data monitoring of the engine control system. The test support equipment module enables a comprehensive interface with the engine control system when installed with the ECU.

A hard disk status testing apparatus, including: a voltage reading module, a controller, an analogue switch, and multiple hard disk slot units. Each hard disk slot unit includes: a hard disk status testing module and a hard disk status indication module. The hard disk status testing modules and the hard disk status indication modules among different hard disk slot units are time-multiplexed, achieving independent control of the hard disk status testing modules of different hard disk slot units and independent control of the hard disk status indication modules of different hard disk slot units. A hard disk status testing method that effectively solves the problem of an increase in the number of pins needed for hard disk status testing and status indication, thus effectively decreasing hardware costs and increasing the utilization rate of pin resources.

Provided is a computer capable of reducing a diagnosis load. For each predetermined diagnosis target node among a plurality of nodes in a neural network, a determination processing unit calculates an expected output value expected as a calculation result of a node calculation process corresponding to the predetermined diagnosis target node, which is obtained when the node calculation process is executed using a predetermined input value. For each diagnosis target node, a generation processing unit generates as a diagnosis program a program for comparing the calculation result of the node calculation process corresponding to the diagnosis target node, which is obtained when the node calculation process is executed by an NN calculation processor using the input value, with the expected output value.