A processing unit can include a performance monitor for monitoring the performance of the processing unit and associated sub-units. The performance monitor includes a logic analyzer, and implements a state machine via state machine data entries stored in a memory associated with the performance monitor. A state machine data entry includes output signals associated with state transitions. The output signals include a next state and a trigger to the logic analyzer. The performance monitor implements logic circuits that determine, based on input signals and the state machine data entries, the next state to transition and associated output signals. If a state transition includes a trigger to the logic analyzer, the trigger is transmitted to the logic analyzer. In response to the trigger, the logic analyzer assembles and samples input signals and stores the sampled input signals into the memory associated with the performance monitor, overwriting the state machine data entries.

A JTAG-based burning device, comprising controllable switches provided between a TDI end of a JTAG host (1) and a first chip and between every two adjacent chips, and further comprising a main controllable switch module (2) provided between each chip and a TDO end of the JTAG host (1). According to a received burning instruction, the JTAG host (1) can control an input end of a corresponding controllable switch to be connected to a corresponding output end thereof, and also control an output end of the main controllable switch module (2) to be connected to a corresponding input end thereof. Hence, the device merely needs to build a circuit to automatically adjust a JTAG link by controlling the connection relationship between the input end and the output end of the corresponding switch, achieving burning of the firmware of different chips or a combination of chips, without manual adjustment, thereby improving the test efficiency, and simplifying a circuit structure.

A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

A memory test system may include a memory apparatus and a test apparatus. The test apparatus may be configured to generate a code distribution of noble cells. The test apparatus may be configured to generate a mass data code distribution and a test result based on the code distribution of noble cells.

A memory test system may include a memory apparatus and a test apparatus. The test apparatus may be configured to generate a code distribution of noble cells. The test apparatus may be configured to generate a mass data code distribution and a test result based on the code distribution of noble cells.

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

A method is provided that provides data analysis for sequence of events reporting in the operation of an industrial process. A digital filter and edge detector are provided that combines a method for excluding known invalid samples and a method for excluding samples taken while the input in the traveling range. The filtering method reduces the overhead on the CPU from managing the sequence of events machine and allows it to focus on performing safety functions.

A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.

A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.