A technique includes accessing, by at least one hardware processor, a recorded request and a recorded response associated with an integration test involving a first computer system and a second computer system. The recorded request was previously issued by the first computer system to the second computer system to cause the second computer system to provide the recorded response. The technique includes, in a virtualized integration test involving the second computer system and initiated using the recorded request, comparing, by the hardware processor(s), the recorded response to a request produced by the second computer system in the virtualized integration test. The technique includes identifying, by the hardware processor(s), an action taken by the second computer system as being likely to be associated with a regression based on the comparison.

Immersive web-based simulator for digital assistant-based applications is provided. A system can provide, for display in a web browser, an inner iframe configured to load, in a secure, access restricted computing environment, an application configured to integrate with a digital assistant. The application can be provided by a third-party developer device. The system can provide, for display in a web browser, an outer iframe configured with a two-way communication protocol to communicate with the inner iframe. The system can provide a state machine to identify a current state of the application loaded in the inner frame, and load a next state of the application responsive to a control input.

An integrated vehicle health management (IVHM) system to resolve equipment-fault related anomalies detected by cyber intrusion detection system (IDS). A benefit of the present system is that it can result in fewer alerts that need manual analysis. A combination of cyber and monitoring with integrated vehicle health management (IVHM) may be a high value differentiator. As a solution gets more mature through a learning loop, it may be customized for different customers in a cost-effective manner, something that might be expensive to develop on their own for most original equipment manufacturers (OEMs). An IVHM symptom pattern recognition matrix may link a pattern of reported symptoms to known equipment failures. This matrix may be initialized from the vehicle design data but its entries may get updated by a learning loop that improves a correlation by incorporating results of investigations.

A testing and verification system for an equivalent physical configuration of an in-flight entertainment and communications system with one or more hardware components includes a virtual machine manager. One or more virtual machines each including a hardware abstraction layer is instantiated by the virtual machine manager according to simulated hardware component definitions corresponding to the equivalent physical configuration of the hardware components. The virtual machines are in communication with each other over virtual network connections. A test interface to the one or more virtual machines generate test inputs to target software applications installed on the virtual machines. A display interface is connected to the virtual machines, with results from the execution of the target software applications responsive to the test inputs are output thereto.

The disclosure relate to detecting performance regressions in software used to control autonomous vehicles. For instance, a simulation may be run using a first version of the software. While the simulation is running, CPU and memory usage by one or more functions of the first version of the software may be sampled. The sampled CPU and memory usage may be compared to CPU or memory usage by each of the one or more functions in a plurality of simulations each running a corresponding second version of the software. Based on the comparisons, an anomaly corresponding to a performance regression in the first version of the software relating to one of the one or more functions may be identified. In response to detecting the anomaly, the first version of the software and the one of the one or more functions may be flagged for review.

In an approach, a processor receives an input indicative of a set of registers, the set of registers being configured for obtaining output data from a design-under-test (DUT) in a field-programmable gate array (FPGA) module. A processor executes a set of instructions for monitoring the output data in the set of registers;. A processor generates data indicative of at least one portion of changes of the output data in the set of registers during the execution of the set of instructions. A processor causes a separate machine to analyze the data via utilizing an interface to send the data to the separate machine.

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

A system for testing a design of a computing component includes an input device configured to receive a request to perform a test of a component, and a testing unit including a simulation of the component. The simulation is configured to output a result indicative of a response to a set of instruction addresses, the set of instruction addresses is acquired from a plurality of addresses, and the plurality of addresses including a plurality of address groups, where each address group is associated with a respective group identifier. The system also includes a plurality of requestors configured to apply the set of instruction addresses to the simulation, where a requestor of the plurality of requestors is configured to select an address for application to the simulation based on a received group identifier and a variably configurable weight value assigned to the received group identifier and the requestor.

An emulation system traverses trace buffers to read data captured from a design under test (DUT). The emulation system receives a request to read at least a portion of DUT data. The emulation system reads a header of the latest sample of the DUT data, where header of each sample of the DUT data includes one or more pointers to a previously stored sample. The samples of the DUT data are partitioned into frames and sectors. The emulation system can identify samples of the DUT data using the pointers in the header of the samples and compare time stamps of the samples against a specified time stamp in the received request. After identifying a sample having the specified time stamp, the emulation system may read the sample for output to the user (e.g., reconstructing a waveform using the sample).

An approach is presented herein to use an in-situ algorithmic decision methodology during each stage of testing before 2C/4C to decide how long to test, how much margin should be used for each device under the test (DUT) to shorten or eliminate 2C/4C testing. Each DUT will be tested differently based on the risk level or the likelihood of failure at 2C/4C. To be able to achieve this, low-level hardware (HW) based sensors (on the printed circuit board assembly (PCBA), in power module, in silicon components, in silicon component complex, etc.) are used to collect telemetry data with a high frequency data acquisition rate during the testing. As testing is ongoing for each DUT, a margin distribution and algorithm modeling is performed in-situ.