A computer-implemented method is provided for redundancy reduction for driving test scenarios. The method includes receiving an original test set of driving scenarios and a driving model which simulates a vehicle behavior under a driving scenario inputted to the driving model. The method includes, for each driving scenario of the original test set, obtaining vehicle dynamics timeseries data as an output of the driving model. The method includes determining similar driving scenarios by comparing driving model outputs. The method additionally includes creating a new test set of driving scenarios by discarding duplicated ones of the similar driving scenarios from the original test set.

A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

A computer-implemented method is provided for redundancy reduction for driving test scenarios. The method includes receiving an original test set of driving scenarios and a driving model which simulates a vehicle behavior under a driving scenario inputted to the driving model. The method includes, for each driving scenario of the original test set, obtaining vehicle dynamics timeseries data as an output of the driving model. The method includes determining similar driving scenarios by comparing driving model outputs. The method additionally includes creating a new test set of driving scenarios by discarding duplicated ones of the similar driving scenarios from the original test set.

Example techniques may be implemented as a method, a system or more non-transitory machine-readable media storing instructions that are executable by one or more processing devices, Operations performed by the example techniques include obtaining data representing results of tests executed by one or more test instruments on an initial set of devices under test (DUTs) in a test system; and using the data to train a machine learning model. The machine learning model is for predicting which of the tests will produce failing results for a different set of DUTs. DUTs in the different set have one or more features in common with DUTs in the initial set.

An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

Example implementations relate to automatically rerunning test executions. Some implementations may capture data during executions of a test. The data may include test status data, test rerun data, test owner data, and/or code committer data. Some implementations may also dynamically determine, for a failed execution of the test, a number of reruns to execute based on the captured data. Additionally, some implementations may cause in response to the dynamic determination, automatic rerun executions of the test until one of the rerun executions passes, the rerun executions being performed up to the number of times.

Test code and test data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing test code and test data in the non-naturally aligned data boundaries as described herein allows test code and data to be replicated throughout a cache memory while preserving double word and quad word boundaries in segments of the replicated test code and test data. Coherency of the processor memory can be tested when the same cache line from the level two (L2) cache is simultaneously in both the level one (L1) instruction cache and the L1 data cache.

A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.