Patent classifications
G06F11/273
DEVICE TESTING ARRANGEMENT
An arrangement for automated testing of mobile devices comprising a learning arrangement for learning how to use test devices that do not match with an earlier already defined test case pattern. In the arrangement the learning arrangement generates instructions for performing a set of tasks. The tasks are then executed in the mobile device being tested. The mobile device provides feedback in form of error/success messages, screenshots, source code, return values and similar. Based on the feedback and earlier accumulated information the learning entity can generate a new set of instructions in order to execute the set of tasks successfully.
MACHINE LEARNING FOR TAPS TO ACCELERATE TDECQ AND OTHER MEASUREMENTS
A test and measurement instrument has an input configured to receive a signal from a device under test, a memory, a user interface to allow the user to input settings for the test and measurement instrument, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to: acquire a waveform representing the signal received from the device under test; generate one or more tensor arrays based on the waveform; apply machine learning to the one or more tensor arrays to produce equalizer tap values; and apply equalization to the waveform using the equalizer tap values to produce an equalized waveform; and perform a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test. A method of testing a device under test includes acquiring a waveform representing a signal received from the device under test, generating one or more tensor arrays based on the waveform, applying machine learning to the one or more tensor arrays to produce equalizer tap values, applying the equalizer taps values to the waveform to produce an equalized waveform, performing a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test.
Regression testing of computer systems using recorded prior computer system communications
A technique includes accessing, by at least one hardware processor, a recorded request and a recorded response associated with an integration test involving a first computer system and a second computer system. The recorded request was previously issued by the first computer system to the second computer system to cause the second computer system to provide the recorded response. The technique includes, in a virtualized integration test involving the second computer system and initiated using the recorded request, comparing, by the hardware processor(s), the recorded response to a request produced by the second computer system in the virtualized integration test. The technique includes identifying, by the hardware processor(s), an action taken by the second computer system as being likely to be associated with a regression based on the comparison.
Regression testing of computer systems using recorded prior computer system communications
A technique includes accessing, by at least one hardware processor, a recorded request and a recorded response associated with an integration test involving a first computer system and a second computer system. The recorded request was previously issued by the first computer system to the second computer system to cause the second computer system to provide the recorded response. The technique includes, in a virtualized integration test involving the second computer system and initiated using the recorded request, comparing, by the hardware processor(s), the recorded response to a request produced by the second computer system in the virtualized integration test. The technique includes identifying, by the hardware processor(s), an action taken by the second computer system as being likely to be associated with a regression based on the comparison.
Processor with debug pipeline
A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
Processor with debug pipeline
A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
Automated functional testing systems and methods of making and using the same
An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.
Automated functional testing systems and methods of making and using the same
An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.
METHOD AND APPARATUS FOR TESTING AI CHIP COMPUTING PERFORMANCE, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM
Provided are a method and an apparatus for testing AI chip computing performance, and a non-transitory computer-readable storage medium. The method includes: forming computing performance result data of a to-be-tested AI chip according to a plurality of items of simulation data formed in a development process of the to-be-tested AI chip; acquiring a function instruction set matched with a to-be-tested service function, wherein the function instruction set is composed of a plurality of instructions in a standard instruction set matched with the to-be-tested AI chip; and predicting computing time required by the to-be-tested AI chip to execute the to-be-tested service function according to the function instruction set and the computing performance result data.
Test equipment interface add-on having a production support equipment module and a selectively removable test support equipment module
Devices, systems, and methods for providing an engine control system configured with a two-part test equipment monitor where at least one part is selectively removable are disclosed. An engine control system for an aircraft includes an electronic control unit (ECU). The ECU is configured to implement a production support equipment module and a selectively removable test support equipment module. The production support equipment module enables restricted data monitoring of the engine control system. The test support equipment module enables a comprehensive interface with the engine control system when installed with the ECU.