The present disclosure relates to systems and methods for matching electronic activities with record objects based on entity relationships. The method can include accessing a plurality of electronic activities, identifying an electronic activity, identifying a first participant associated with a first entity and a second participant associated with a second entity, determining whether a record object identifier is included in the electronic activity, identifying a first record object of the system of record that includes an instance of the record object identifier, and storing an association between the electronic activity and the first record object. The method can include determining a second record object corresponding to the second entity, identifying, using a matching policy, a third record object linked to the second record object and identifying a third entity, and storing, by the one or more processors, an association between the electronic activity and the third record object.

An electronic element includes: a module for storing reference data; a module for receiving data from a processor; a module for verifying the received data by comparison by way of reference data; and a module for transmitting an instruction to cut off supply of the processor, the supply cutoff instruction being transmitted after occurrence of a failure event, the failure event being an absence of reception of data or a failure in verifying the data. A system including such an electronic element and a method for monitoring a processor by the electronic element are also described.

Systems, apparatuses, and methods for dynamic graphics processing unit (GPU) register allocation are disclosed. A GPU includes at least a plurality of compute units (CUs), a control unit, and a plurality of registers for each CU. If a new wavefront requests more registers than are currently available on the CU, the control unit spills registers associated with stack frames at the bottom of a stack since they will not likely be used in the near future. The control unit has complete flexibility determining how many registers to spill based on dynamic demands and can prefetch the upcoming necessary fills without software involvement. Effectively, the control unit manages the physical register file as a cache. This allows younger workgroups to be dynamically descheduled so that older workgroups can allocate additional registers when needed to ensure improved fairness and better forward progress guarantees.

Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes a first performance counter to increment upon occurrence of a first type of event in the processor and a second performance counter to increment upon occurrence of a second type of event in the processor. The processor is to reset the second performance counter in response to the first performance counter reaching a first limit.

Resource utilization data for a set of system components of a computing system is collected. The resource utilization data includes performance records for a set of jobs. By analyzing the collected resource utilization data for the set of system components, a resource allocation is identified for a particular job of the set of jobs. A first execution time for the particular job is determined based on the resource allocation for the particular job and the resource utilization data for the set of system components. A location at which to execute the particular job is determined based on how the particular job has been executed at the location previously. The first execution time may be a time when the computer system achieves a resource availability threshold with respect to the resource allocation. Aspects are also directed toward performing the particular job at the first execution time.

In the present invention, a management system has a storage device and a processor. The storage device holds an information processing program for controlling information pertaining to a storage system by utilizing a database. The processor executes an update program that updates the information processing program and the database utilized by the information processing program. The update program calculates an estimated update time needed to update the information processing program and the database on the basis of the size of at least a portion of the database utilized by the information processing program before being updated and the structure of the database utilized by the information processing program after being updated, and outputs the estimated update time thus calculated.

A disclosed load estimation method includes: collecting run information of a processor being executing a predetermined program; specifying execution status of the processor based on the collected run information; and estimating a load of the predetermined program based on a result of comparison between the execution status of the processor and execution characteristics of the processor. Each of the execution characteristics is stored in association with a load level of the predetermined program.

A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.