Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

The present disclosure relates to a non-transitory computer-readable recording medium storing an analysis program that causes a computer to execute a process. The process includes sampling an instruction address of one of instructions included in a program during execution of the program, identifying a first function that includes the sampled instruction address in an address range, rewriting mark information associated with the identified first function, identifying first information corresponding to the instruction address of the first function among a plurality of first information based on the rewritten mark information, identifying second information corresponding to the instruction address of the first function among a plurality of second information based on the rewritten mark information, storing the first information and the second information in a memory, and analyzing performance of the program based on the first information and the second information stored in the memory.

Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

A description of a snapshot to be generated is received by a local media controller of a memory device, from a memory sub-system controller. The description comprises a memory address range of a memory device. Responsive to detecting a triggering event, a snapshot of the memory address range of the memory device is generated in view of the description. The snapshot is stored to a destination address. The memory sub-system controller is notified of the triggering event.

A method for monitoring the free space of a stack of a microcontroller during the execution of a process using spaces of the stack from a start address to an end address of the stack, in which the method includes: in a prior step, writing N keys in the stack at N addresses of the stack, the memory space between two consecutive keys decreasing in a direction from the start address to the end address of the stack; and, in a step of executing the process, saving the address of the current key, corresponding to the address of the existing key, among the N keys, that is closest to the stack start address.

An apparatus to facilitate watchpoints for debugging in a graphics environment is disclosed. The apparatus includes processing resources to perform graphics operations using a plurality of threads; and load store pipeline hardware circuitry coupled to the processing resources to: configure a watchpoint register with a value of a watchpoint address, the watchpoint address comprising an address of a memory location in the processor; receive a memory access request from a thread of the plurality of threads; determine, using the watchpoint register, whether the memory access request is requesting access to the watchpoint address; and responsive to the memory access request requesting access to the watchpoint address, return an exception payload to the thread, the exception payload comprising watchpoint details corresponding to the watchpoint address and a scoreboard identifier (SBID) associated with the memory access request.

An apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. The apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token; receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and return the SBID associated with the memory access response and fault details of the page fault error condition to a debug register of the thread.

Auditing information is captured from a processing stack of an invoked application. An annotation customized for that invocation context is processed to filter and/or add additional audition information available from the processing stack. The customized auditing information is then sent to a destination based on a processing context of the invoked application when the invoked application completes processing. In an embodiment, the customized auditing information is housed in a data store and an interface is provided for customized query processing, report processing, event processing, a notification processing.

The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Auditing information is captured from a processing stack of an invoked application. An annotation customized for that invocation context is processed to filter and/or add additional audition information available from the processing stack. The customized auditing information is then sent to a destination based on a processing context of the invoked application when the invoked application completes processing. In an embodiment, the customized auditing information is housed in a data store and an interface is provided for customized query processing, report processing, event processing, a notification processing.