A system includes one or more processors in communication with a memory and configured to receive a task to probe a portion of the memory associated with a version of a binary file during execution of the binary file. The task includes a portion of object code and a hash identifier, both associated with the version of the binary file. A database mapping hash identifiers to debug information associated with installed binary files is accessed. Debug information for the version of the binary file associated with the hash identifier is retrieved. A probing application is built using the debug information and the portion of object code. Upon execution of the version of the binary file, the probing application places the object code into the portion of the memory.

Systems and methods for automatically recovering from software regression in a cloud computing environment. One example method includes determining, with an electronic processor, that a batch software update has been applied to the cloud computing environment. The method includes, in response to determining that a batch software update has been applied, transmitting a problem request to an event listener server. The method includes receiving, from the event listener server, a problem statement including a stack trace. The method includes determining, based on the stack trace, a software feature indicator. The method includes transmitting the software feature indicator to a root cause analyzer. The method includes receiving, from the root cause analyzer, a change list indicator and a relevancy score associated with the change list indicator. The method includes performing a mitigation action based on the change list indicator when the relevancy score exceeds a relevancy threshold.

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.

A method of analyzing a performance of a microservices-based application comprises generating a plurality of traces from a plurality of spans associated with the microservices-based application. The method also comprises generating a plurality of data sets each associated with a respective analysis mode of a plurality of analysis modes using the plurality of traces, wherein each analysis mode extracts a different level of detail for analyzing the performance of the services in the application from the plurality of spans. Further, the method comprises selecting, based on a first user query, a first analysis mode from the plurality of analysis modes for generating a response to the first user query. The method also comprises accessing a data set of the plurality of data sets that is associated with the first analysis mode and generating the response to the first user query using the data set associated with the first analysis mode.

A method and apparatus for collecting debug and crash information are described. In one embodiment, a system comprises one or more compute engines an external interface; a non-volatile memory coupled to the external interface and operable to store captured information, wherein the captured information comprises one or both of debug information and crash information; a first trace aggregator coupled to the non-volatile memory and the one or more compute engines to capture the one or both of debug information and crash information from at least one of the one or more compute engines in response to a crash of the system; and a controller, coupled to the non-volatile memory and the first trace aggregator, to cause captured information to be sent from the first trace aggregator to the non-volatile memory and to subsequently control transfer of the captured information stored in the non-volatile memory to the external interface.

A virtualization platform that provides a systematic, transparent and local testing of components hosted by the virtualization platform in their integrated context. The virtualization platform comprises integrated interceptor modules connected to the components via communication channels, each interceptor module being interposed in the communication channel connecting two components, and an integrated analyzing device connected to the interceptor modules and comprising a control device and a testing device. The control device is configured to put each interceptor module in an operational mode selected out of a set of predetermined operational modes including a testing mode. The testing device is configured to locally test the components connected to the interceptor modules being put in the testing mode.

The present disclosure includes apparatuses and methods related to performing a debug operation on an artificial intelligence operation. An example apparatus can include a number of memory arrays and a controller, wherein the controller is configured to perform an artificial intelligence (AI) operation on data stored in the number of memory arrays and perform a debug operation on the AI operation.

The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Techniques are provided for recording service invocation traffic in a format that is suitable for subsequent replay, perhaps in a different environment. In one technique, a computing device records invocation traffic. The computing device receives a first request that is directed to a first service. In response to receiving the first request, one or more computers store an identifier of the first request into a second request. After storing the identifier into the second request, the computing device causes the second request to be sent to a second service. After causing the second request to be sent to the second service, the computing device receives, from the second service, a response that contains the identifier of the first request. The one or more computers store, in a single record, the first request, the second request, and the response.