Patent classifications
G06F11/364
Annotated deterministic trace abstraction for advanced dynamic program analysis
A virtual machine that includes a plurality of processes executes on a computer processor. A record-replay file, trace annotations, and an application program interface request are received into the computer processor. The trace annotations and application program interface request are translated into record-replay commands. The record-replay commands capture data from the record-replay file, and the captured data can be accessed via a programmatic interface.
Contextual drill back to source code and other resources from log data
A system receives real-time log messages from an executing process that experiences a runtime error. Information such as a filename and line number for the underlying source code may be embedded in the log messages using compiler macros. When the log messages are received, a developer URL may be generated that links a developer workstation directly to the underlying source code file and line number in a source code repository. A support URL may also be generated with a link to a support center and an embedded search string that retrieves resources that are known to address the process error.
Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (HLS) code
High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen. This enables traceability of the code execution on the screen and printf/scanf statements output can be observed without any challenges.
Microchip with on-chip debug and trace engine
A microchip includes a central processing unit (CPU) configured to execute a software application. The microchip further includes an Ethernet interface configured to transmit Ethernet packets to and receive Ethernet packets from an external debugging entity. The microchip further includes an on-chip debug and trace module configured to transform debugging data and trace data from the CPU into a stream of Ethernet packets, and to provide the stream of Ethernet packets to the Ethernet interface for transmitting the stream of Ethernet packets to the external debugging entity.
GENERATING DEBUGGING INFORMATION FOR QUERY PLAN STEPS
A query plan includes steps to implement a query and debug steps interleaved among the steps. An execution engine of a database system executes each step of the query plan to realize the query. The execution engine executes each debug step of the query plan to generate debugging information for the step preceding the debug step within the query plan. The debugging information is queryable.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM
An information processing device and information processing method with improved error tolerance are implemented. There is included a data processing unit that executes lockstep processing in which a plurality of processing systems executes the same task and error verification is performed by comparing execution results. In a case where an error is detected in the lockstep processing, the data processing unit increases supply voltage to a CPU circuit system that executes the task, processing of lowering a supply clock, or the like, as control for improving noise tolerance of the CPU circuit system, and moreover, performs re-execution processing of the task by using more processing systems than the processing systems before the error detection.
Trace anomaly grouping and visualization technique
A trace anomaly grouping and visualization technique logically groups traces with anomalies to cases to enable software developers to monitor, diagnose and visualize the anomalies, as well as to solve the anomalies during application development and production. A client library of an investigative platform collects signals from traces (trace signal information). The technique organizes (groups) related trace signals of methods with anomalies (e.g., exceptions, performance abnormalities such as slowness) into datasets (denominated as “cases”) based on common cause for an anomaly and correlates the signals to identify a case. The collected information may be used to differentiate between root causes of the anomalies using a comparative visualization of traces displayed on a standard user interface of the investigative platform. As such, the technique facilitates an understanding of differences among traces of executable code that resulted in the failure and traces without failure by providing the ability to comparatively examine views of those traces displayed on the standard UI. Signals of two or more traces may be selected and displayed side-by-side for comparison. The traces may be selected from a general notion of a healthy trace and a failed trace.
Post simulation debug and analysis using a system memory model
According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform.
Automatic Creation of Structured Error Logs from Unstructured Error Logs
An error logging system is provided that is configured to automatically create a type introspection database from a compiled application that was written using the C programming language. During execution of the application, if there is an error, the executing application will generate an unstructured error log which is passed to an error logging system. The type introspection database enables the error logging system to parse the unstructured error log to create a corresponding structured error log. The error logging system includes generic display, search, and share functions. The display function is configured to display the name, value, and type, of every attribute in each data structure. The search function provides a way to determine if the structured error log satisfies a selection criteria specified on one or more attributes of the data. The share function enables the error logging system to export the structured error logs.
Software bug reproduction
Example methods and systems for software bug reproduction. One example method may comprise obtaining log information associated with multiple transactions processed by a control-plane node to configure a set of data-plane nodes and transform an initial network state to a first network state; and configuring a replay environment that is initialized to the initial network state, and includes a mock control-plane node and a set of mock data-plane nodes. The method may also comprise, based on the log information, replaying the multiple transactions using the mock control-plane node to configure the set of mock data-plane nodes and transform the replay environment from the initial network state to a second network state. Based on a comparison between the first network state and the second network state, a determination may be made as to whether a software bug is successfully reproduced in the replay environment.