An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.

A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Methods, media, and systems for detecting anomalous program executions are provided. In some embodiments, methods for detecting anomalous program executions are provided, comprising: executing at least a part of a program in an emulator; comparing a function call made in the emulator to a model of function calls for the at least a part of the program; and identifying the function call as anomalous based on the comparison. In some embodiments, methods for detecting anomalous program executions are provided, comprising: modifying a program to include indicators of program-level function calls being made during execution of the program; comparing at least one of the indicators of program-level function calls made in the emulator to a model of function calls for the at least a part of the program; and identifying a function call corresponding to the at least one of the indicators as anomalous based on the comparison.

A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

This disclosure involves debugging code for resource-constrained intelligent devices contemporaneously with executing object code on the intelligent device. For example, object code is transmitted to a radio device. A program counter entry is provided from the radio device to a computer via a communication link contemporaneously with a pause in execution of the object code at the radio device. A correspondence between the program counter entry and a portion of assembly code, which was used to generate the object code, is identified and is used to generate a list of additional program counter entries for pausing the object code's execution. The list is provided from the computer to the radio device and is used to pause the object code's execution at the radio device. Log data is provided from the radio device to the computer for display after pausing the object code's execution at one of these program counter entries.

A method, apparatus, and virtual computer system for testing application software. A first operating system of a first operating type is run on a first processor of a first processor type in a physical computer system. A virtual machine that emulates a second processor of a second processor type is run on the first processor. A second operating system of a second operating type is run on the virtual machine with the virtual machine running on the first processor. The first processor running the first operating system and the virtual machine running the second operating system together form the virtual computer system. A tool qualifier module performs verification of an application testing tool on the virtual machine using tool qualification data to qualify the application testing tool before the application testing tool is run using the second operating system on the virtual machine to test an application program.

An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Immersive web-based simulator for digital assistant-based applications is provided. A system can provide, for display in a web browser, an inner iframe configured to load, in a secure, access restricted computing environment, an application configured to integrate with a digital assistant. The application can be provided by a third-party developer device. The system can provide, for display in a web browser, an outer iframe configured with a two-way communication protocol to communicate with the inner iframe. The system can provide a state machine to identify a current state of the application loaded in the inner frame, and load a next state of the application responsive to a control input.