Immersive web-based simulator for digital assistant-based applications is provided. A system can provide, for display in a web browser, an inner iframe configured to load, in a secure, access restricted computing environment, an application configured to integrate with a digital assistant. The application can be provided by a third-party developer device. The system can provide, for display in a web browser, an outer iframe configured with a two-way communication protocol to communicate with the inner iframe. The system can provide a state machine to identify a current state of the application loaded in the inner frame, and load a next state of the application responsive to a control input.

An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Emulation has become a critical method for the initial phase of verification and validation processes. However, achieving interoperability between emulation systems and ensuring credibility of results currently require significant efforts. This disclosure relates to a system and method for providing an emulation as a service (EaaS) framework for communication networks. The EaaS framework provides discoverable services that are readily available on-demand and deliver a choice of applications in a flexible and adaptive manner. The EaaS framework is used for discovery, composition, execution, and management of emulation services. The EaaS framework defines user-facing capabilities (front-end) and underlying core functional infrastructure (back-end). The front end provides access to a large variety of emulation capabilities from which the user is able to select the services and track the experiences.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

A continuous integration framework for developing software for transaction processing and method for using the same are described. In one embodiment, the method comprises generating a trusted artifact with a forward immutable continuous integration (CI) implemented as a build pipeline, wherein the artifact comprises updated software comprising payment processing code with an EMV vector kernel for processing of EMV-based card present transactions; and in response to the software update, performing end-to-end testing of EMV card present transactions using code commits from one or more code repositories, wherein the end-to-end testing comprises executing the code commits that includes executing payment processing code for processing EMV-based card present transactions with an EMV vector kernel and one or more emulated EMV cards, and running tests against the executing code commits to validate behavior the payment processing code including the EMV vector kernel, wherein the tests comprise running one or more emulated EMV cards against the vector kernel as part of one or more emulated EMV-based card present transactions and monitoring communications related to the one or more emulated EMV-based card present transaction communications.

A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

A method for debugging a logic system design including a target module to be debugged. The method includes receiving a first gate-level netlist associated with the logic system design and a second gate-level netlist associated with the target module that are generated based on a description of the logic system design, obtaining runtime information of an input signal of the target module by running the first gate-level netlist, and obtaining runtime information of the target module by running the second gate-level netlist based on the runtime information of the input signal of the target module.

The present disclosure relates to a computing platform and a relative computer implemented method for synchronize the prototype execution and simulation of hardware devices. The computing platform (1) comprises a debugger module (2), a memory (3) for storing instructions and data of a computer program; a CPU (4) configured for executing said computer program; said debugger module (2) being in signal communication with said memory (3) through a first debugger channel (dbg2Mem). Characteristic of the computing platform is that it comprises at least one pin (7) and at least one trigger point module (8), said at least one pin (7) being connectable to an electronic device (Ext) that is external to the computing platform; said at least one trigger point module (8) being in signal communication with said at least one pin (7) through a first trigger channel (tgr2pin), said debugger module (2) through a second trigger channel (t2d), said CPU (4) through a third trigger channel (tProbe), said at least one trigger point module (8) having a first register (10a) for storing a first trigger point (RefStartTrgPnt) that corresponds to a first instruction of said program to be monitored.

An image processing apparatus includes a host controller that controls a hardware resource, a guest controller, an emulator that is provided between the host controller and the guest controller and allows the guest controller to control the hardware resource, and a changer that changes an HDL program, wherein the guest controller includes a guest driver, the emulator includes a device emulator that emulates the hardware resource by executing the changed HDL program, and a switcher that switches control to any one of a first control for controlling the host controller in accordance with control of the hardware resource by the guest driver and allowing the hardware resource to be controlled, and a second control for controlling the device emulator in accordance with the control of the hardware resource by the guest driver.