In one embodiment, a computing system may access design data of a printed circuit board to be produced by a manufacturing process. The system may determine one or more corrections for the design data of the printed circuit board based on one or more correction rules for correcting one or more parameters associated with the printed circuit board. The system may automatically adjust one or more of the parameters associated with the design data of the printed circuit board based on the one or more corrections. The adjusted parameters may be associated with an impedance of the printed circuit board. The one or more corrections may cause the impendence of the printed circuit board to be independent from layer thickness variations of the printed circuit board to be produced by the manufacturing process.

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

A design program for causing a computer to execute a process including: selecting, based on design data of a printed wiring board, a first transmission line and a second transmission line among transmission lines provided in the printed wiring board; adjusting a first wiring length between a first via in the first transmission line and a third via in the first transmission line, a second wiring length between a second via in the second transmission line and a fourth via in the second transmission line, a length of the first via, a length of the second via, a length of the third via, or a length of the fourth via such that a phase of first crosstalk noise generated between the first via and the second via is inverted between the third via and the fourth via; and outputting the design data corrected based on the adjustment in the board.

Various embodiments disclosed herein relate to a building automation controller and related method and storage medium including a processor configured, through at least execution of a distributed computer program, to: receive sensor data generated by a sensor, wherein the sensor data is indicative of a state of a defined space, identify an action to be performed by a device to affect the state in accordance with an operating characteristic for the defined space, determine that the device is attached to a second controller of a plurality of additional controllers, and transmit to the second controller, an indication that the action is to be performed by the device, wherein: the distributed computer program is configured to be distributed among the processor and the plurality of additional controllers and, the processor is further configured to apportion work to be performed by the computer program between at least the additional controllers.

Disclosed are a method of PCB sectional preshrinking, a device, an equipment and a computer-readable storage medium. The method includes: obtaining a PCB raw data and a preset accuracy requirement; determining a preshrinking compensation value according to the PCB raw data and the preset accuracy requirement; determining a first sectional length according to the PCB raw data and the preshrinking compensation value; determining a preshrinking compensation ratio according to the preshrinking compensation value and the first sectional length; determining a second sectional length according to the PCB raw data, the first sectional length and the preshrinking compensation ratio; and determining an optimization preshrinking design length according to the first sectional length and the second sectional length.

Tools and techniques are described to attach a device to a controller, whereby the controller analyzes the device inputs, looks up information about the device in a database, and then determines which inputs on the device match the defined device inputs. It then may translate information received from the device into an intermediate language. It may also use the information received from the device, the location of the device, and information about the device to create a digital twin of the device.

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an interposer disposed on a portion of the package substrate. A first integrated circuit (IC) chip is disposed on the interposer. A first memory device is disposed on the interposer and includes a first port interface including an interposer-compliant mechanical interface for coupling to the first IC chip via a first set of traces formed in the interposer. A second port interface includes a non-interposer-compliant mechanical interface for coupling to an off-interposer device. Transactions between the first IC chip and the off-interposer device pass through the first port interface and the second port interface of the first memory device.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a logic base die for inclusion in a chiplet-based multi-chip module (MCM) is disclosed. The logic base die includes a first port interface for coupling to an interface beachfront of a first integrated circuit (IC) chiplet. The first port interface is to receive data of a first bandwidth via the interface beachfront via a first set of traces formed in a micro-bump advanced-package routing layer. A memory port provides a first portion of the first bandwidth to at least a first memory stack configured for positioning on the logic base die. A second port interface couples to the first port interface and utilizes a second portion of the first bandwidth.

In one embodiment, an automated high-speed X-ray inspection system may identify reference objects for an object of interest to be inspected. Each reference object may have a same type and components as the object of interest. The system may generate a reference model for the object of interest based on X-ray images of the reference objects. The system may determine whether the object of interest is associated with one or more defects by comparing an X-ray image of the object of interest to the reference model. The defects may be characterized by one or more pre-determined defect models and may be classified into respective defect categories based on the pre-determined defect models.