Conducting automatically a process failure mode and effect analysis, PFMEA, for a factory adapted to produce a product in a production process using a meta model, MM, stored or loaded in a data storage. The stored meta model, MM, comprises abstract factory model elements modeling an abstract factory, AF, including one or more service declarations modeling abstract services across different factories, wherein each service declaration comprises failure mode declarations for different failure modes.

A computer-implemented method for computationally determining ventilation efficiency when generating a building design comprises: generating a first three-dimensional (3D) mesh based on a first 3D building model; performing a first fluid dynamic computer simulation based on the first 3D mesh and first environmental data associated with the first 3D building model to generate a first output data set; and computing, based on the first output data set, a first value for a ventilation performance metric that is associated with the first 3D building model.

A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.

A method includes receiving measurement data from multiple sensors positioned along a delivery line that delivers a liquid as a gas to one of a gas panel or a processing chamber; simulating, using a computer-generated model, one or more process parameters associated with the delivery line and a plurality of heater jackets positioned around the delivery line; comparing the measurement data with values of the one or more process parameters; and determining, based on at least a threshold deviation between the measurement data and the values of the one or more process parameters, that a fault exists that is associated with maintaining temperature within the delivery line consistent with a gaseous state of the liquid.

System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for simulating a concrete mixture. One of the methods includes obtaining an optical characterization of physical particles, generating a multispherical approximation of the physical particles, the multispherical approximation having reduced dimensionality compared to the optical characterization, simulating an aggregate mixture by applying the multispherical approximation of the particles to a physics simulator to obtain a predicted performance of the proposed aggregate mixture, selectively altering the aggregate mixture based on a comparison with performance metrics and simulating the altered aggregate mixture until the predicted performance satisfies the performance metrics to obtain a final aggregate mixture, and outputting the final aggregate mixture.

A method for identifying observation points for integrated circuit (IC) testing includes receiving a netlist for an IC that includes a first subcircuit and a second subcircuit; determining, from the netlist, one or more observation points, each determined observation point corresponding to an output node which provides observability, into at least the first subcircuit, of an effective number of gates above a specified threshold; and inserting a design for test element into a layout file of the IC at each determined observation point. Observation points can be determined by transforming the netlist into a node graph; assigning a same initial value to a value field of each node; and propagating values in the value fields of the nodes until all nodes with a succeeding edge have a value of zero in their value fields.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Provided are techniques for digital twin functional and non-functional simulation testing. An indication is received that digital twin functional and non-functional simulation testing is to start for an application being developed, where a first portion of code for the application has been developed and a second portion of the code for the application has not been developed. Application data and an application landscape are retrieved. The digital twin functional and non-functional simulation testing is performed to identify which functional and non-functional requirements are not being met by the first portion of the code. For the functional and non-functional requirements that are not being met, suggestions are provided for at least one of the first portion and the second portion to meet one or more of the functional and non-functional requirements. One or more of the suggestions are implemented.

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.