An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.

Methods for modifying power use of a semiconductor device include receiving, at one or more processors, an activity stream of a simulation of a semiconductor device, the activity stream comprising a stream of signals. Using the one or more processors, integrated circuit actions are recognized from the activity stream, each integrated circuit action representing an abstraction of work done by the semiconductor device. The processor(s) determine one or more values associated with the integrated circuit actions. A model of power use is generated for the semiconductor device, the model based at least in part on the recognized integrated circuit actions and the associated values. Based on an output of the model, power use of the semiconductor device is modified. Other methods and systems related to determining, modeling, and predicting power/energy use of semiconductor devices are also disclosed.

The present invention relates to a method and a system for processing building energy information. The method includes the following steps: inputting data of a building information model into building energy simulation software; automatically selecting a building category or manually selecting a building category from a group of building categories provided by the building energy simulation software; in response to the selected building category, inputting a plurality of parameters into a lookup table of the building energy simulation software in accordance with a database of the building energy simulation software; and generating an estimation of a building's energy consumption through a calculation by the building energy simulation software based on the parameters.

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

A chip design method, a chip design device, a chip, and an electronic device are provided. The chip design method includes: determining at least one power state of the chip, one power state of the at least one power state including switch states of respective power domains on the chip in a chip operation mode, and the at least one power state including a first power state; determining control signals sent by changed power domains in the respective power domains in a case where a power state of the chip is switched to the first power state, in a case where the power state of the chip is switched to the first power state, switch states of the changed power domains changing; and analyzing timing dependency between the control signals to determine timing dependency between power domains to which the control signals act in the first power state.

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.