G06F119/18

Support method, server, and design support system

A design support system for permitting a design that easily meets desired conditions regarding an entire item group is provided. An automatic estimation system acting as the design support system comprises: an item recognition section that recognizes each of the items included in the item group by individually recognizing elements making up the item; a designated condition recognition section that recognizes a designated condition from the manufacturing conditions; and a recommended-to-be-examined element recognition section that recognizes, with respect to the designated condition recognized, the element corresponding to any of the manufacturing conditions that is recommended to be examined for changes. The recommended-to-be-examined element recognition section displays a model of the item group by highlighting the element for which the manufacturing condition is recommended to be examined for changes.

Support method, server, and design support system

A design support system for permitting a design that easily meets desired conditions regarding an entire item group is provided. An automatic estimation system acting as the design support system comprises: an item recognition section that recognizes each of the items included in the item group by individually recognizing elements making up the item; a designated condition recognition section that recognizes a designated condition from the manufacturing conditions; and a recommended-to-be-examined element recognition section that recognizes, with respect to the designated condition recognized, the element corresponding to any of the manufacturing conditions that is recommended to be examined for changes. The recommended-to-be-examined element recognition section displays a model of the item group by highlighting the element for which the manufacturing condition is recommended to be examined for changes.

Pattern centric process control

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

Fast topology bus router for interconnect planning

A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.

Computational platform for quantum structures

The present disclosure provides a computational platform for quantum structures. The computational platform includes an input module configured to receive parameter information corresponding to a quantum structure, and a processor programmed to carry out instructions stored in a computer-readable medium. The instructions include receiving, using the input module, the parameter information corresponding to the quantum structures, and generating a quantum structure model based on the parameter information received. The instructions also include determining at least one property of the quantum structure, and generating a report indicative of the at least one property determined. The computational platform also includes an output module for providing the report.

Methods and systems for printed circuit board design based on automatic corrections

In one embodiment, a computing system may access design data of a printed circuit board to be produced by a manufacturing process. The system may determine one or more corrections for the design data of the printed circuit board based on one or more correction rules for correcting one or more parameters associated with the printed circuit board. The system may automatically adjust one or more of the parameters associated with the design data of the printed circuit board based on the one or more corrections. The adjusted parameters may be associated with an impedance of the printed circuit board. The one or more corrections may cause the impendence of the printed circuit board to be independent from layer thickness variations of the printed circuit board to be produced by the manufacturing process.

Learning device, inference device, and learned model

A learning device for performing a machine learning based on a learning model using data input to an input layer, includes: a calculation part configured to calculate a predetermined number of features, in which simulation data as a result of simulating semiconductor manufacturing processes by setting environmental information inside a process vessel in which the semiconductor manufacturing processes are performed and using a predetermined component provided in the process vessel as a variable, and XY coordinates parallel to a plane of a wafer are associated with each other; and an input part configured to input the calculated predetermined number of features to the input layer.

Orthopedic device, method, and system for making an orthopedic device
11648142 · 2023-05-16 · ·

An orthopedic device comprises a body having a monolithic structure and arranged to form a closed circumference in a secured configuration, the body having a predetermined shape in an unsecured configuration. The body is formed continuously without interruption from at least one polymeric material. A method for making the orthopedic device includes providing a schematic including a model representing a body part for which the orthopedic device is intended, providing at least one array of coordinates and indicia corresponding to the coordinates proximate to the model at a plurality of locations along the model, and providing a scale set corresponding to the coordinates. The dimensions obtained from measuring the body part may be used to form a custom-shaped orthopedic device.

Integrated circuit and method of forming same

A method of forming an integrated circuit includes placing a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. Placing the first cell layout design includes placing a first active region layout pattern adjacent to a first cell boundary, placing a second active region layout pattern adjacent to a second cell boundary, and placing a first set of active region layout patterns between the first and second active region layout patterns, according to a first set of guidelines. The first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength. In some embodiments, the first, second and first set of active region layout patterns extend in the first direction, and are on a first layout level.

Method of manufacturing semiconductor device and system for same

A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.