A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, when updating a target firmware, a memory system may receive, from a host, a temporary firmware for increasing the size of a buffer from a preset first size to a second size equal to or greater than the size of the target firmware, may load and execute the temporary firmware into a processor, may receive the target firmware from the host and write the target firmware to the buffer, and may write the target firmware to the memory device.

Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.

The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

A mobile device (100) includes a processing device (140), a random access memory, RAM, (150) and an embedded mass storage device (160). A first interface (IF1) is provided between the processing device (140) and the RAM (150). The first interface (IF1) supports access of the processing device (140) to the RAM (150). The mass storage device (160) includes a controller (170) and a non-volatile flash memory (180). A second interface (IF2) is provided between the controller (170) and the flash memory (180). The second interface (IF2) supports access of the controller (170) to the flash memory (180). A third interface (IF3) is provided between the controller (170) and the processing device (140). The third interface (IF3) supports access of the controller (170) to the RAM (150).

Example implementations disclosed herein include techniques for a ready only bufferpool for use in local nodes of a multi-node computing system. Read only transactions executed by a processor can reference a ready only bufferpool resident in a VRAM on the same node. If the desired data page is in the bufferpool the transaction can immediately read data records from the cached data pages. If the desired data page is not in the bufferpool, then the transaction can cause a copy of a corresponding data page in a secondary memory to be installed in the bufferpool. The bufferpool can include more than one copy of a data page simultaneously to handle and prevent cache line misses. Data page are dropped from the bufferpool based on an incrementing per data page counter.

A method may include storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A system may include a processor, a volatile memory coupled to the processor, and a persistent memory coupled to the processor. The processor may be configured to execute procedures including storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A method may include storing at least a portion of a transient part of a persistent data structure in volatile memory, and storing at least a portion of a persistent part of the persistent data structure in persistent memory.

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.

Disclosed in some examples are methods, systems, memory devices, memory controllers, and machine-readable mediums which provide for reserving physical memory device resources to specific execution units. Execution units may include processes, threads, virtual machines, functions, procedures, or the like. Physical memory device resources may include channels, modules, ranks, banks, bank groups, and the like. For example, a physical memory device resource that is reservable may be a smallest unit that allows for parallel access with another of the same size unit.

Methods, apparatus, systems and articles of manufacture are disclosed to utilize non-volatile memory for computer system boot. An example processor platform includes a non-volatile memory coupled to a processing unit via a bus, and a microcontroller to: configure the processing unit to store, on the non-volatile memory, a heap and a stack for execution of boot code, and configure the processing unit to execute the boot code stored on the non-volatile memory.