Methods and systems are disclosed for optimizing record placement in a graph by minimizing fragmentation when writing data. Issues with fragmented data within a graph database are addressed on the record level by placing data that is frequently accessed together contiguously within memory. For example, a dynamic rule set may be developed based on dynamically analyzing access patterns of the graph database, policies, system characteristics and/or other heuristics. Based on statistics regarding normal query patterns, the systems and methods may identify an optimal position for certain types of edges that are often traversed with respect to particular types of nodes.

Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

A command pertaining to a non-volatile memory device on a memory sub-system is received from a host system. A portion of the non-volatile memory device has an association with the host system. In response to determining that the command is a dissociate instruction to dissociate the portion of the non-volatile memory device on the memory sub-system with the host system, remove the association of the portion of the non-volatile memory device on the memory sub-system with the host system.

A system and method of device assignment includes receiving an assignment request to assign a device to a plurality of guest virtual machines. The plurality of guest virtual machines includes a first guest virtual machine with a first guest memory having a first physical address and a second guest virtual machine with a second guest memory having a second physical address. The method includes selecting a first bus address offset and a second bus address offset different from the first bus address offset. The method includes sending, to the first guest virtual machine, the first bus address offset, and sending, to the second guest virtual machine, the second bus address offset. The method includes updating a mapping to the first physical address to include the first bus address offset, and updating a mapping to the second physical address to include the second bus address offset.

A method of providing a file system for an electronic device includes organizing a plurality of Non-Volatile Dual In-Line Memory Module-Ps (NVDIMM-Ps) of a memory device of the electronic device into a plurality of groups based on location information of the NVDIMM-Ps, and creating a single File System Instance (FSI) for each group included in the plurality of groups.

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

A memory system includes a first memory device suitable for inputting and outputting data through a serial interface, a second memory device suitable for inputting and outputting the data through a parallel interface, and a controller suitable for detecting an access pattern of the data, selecting one of the first and the second memory devices based on the detected access pattern, and controlling the selected memory device to store the data.

A controller configures a map table including a map entry associating different address schemes with each other. The controller is configured, for performing map table configuration, to find a target map entry among previous map entries in the map table, merge the current map entry into the target map entry to generate a merged map entry when the target map entry is found, and store the merged map entry in the map table. The target map entry and a current map entry include at least some information which is overlapped.

A memory device is provided. The memory device comprises: a plurality of memory cells, each memory cell being programmable to at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the memory cell, the plurality of memory cells comprising a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of said at least two logic states; a memory controller coupled to the plurality of memory cells and configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation to assess the logic state thereof.

The memory controller is further configured to: apply the reading voltage to the memory cells of the second group to assess the logic state thereof; if the logic state of at least one memory cell of the second group is assessed to be different from said predefined logic state, perform a refresh operation of the memory cells of the first group by applying thereto a recovery voltage higher than the reading voltage to assess the logic state thereof and then reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.