According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

Dynamic address allocation of multiple device instances of an improved inter-integrated circuit (I3C) target device by an I3C controller device is disclosed. A first device instance is configured to receive a command and a clock signal from the I3C controller device, and further receive a first status signal that is indicative of a first device instance ID of the first device instance. The first device instance is further configured to decode the command based on the first status signal and the clock signal, and generate a response that includes the first device instance ID. The I3C controller device is configured to allocate a dynamic address to the first device instance based on the response. The first device instance is then configured to generate and provide a second status signal to a second device instance for facilitating dynamic address allocation of the second device instance.

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

A system of electronic modules is described, along with a method of assigning addresses to the modules. The modules are communicatively connected along a communication path, and are also communicatively connected to an address bus. Adders are positioned along the address bus, with at least one adder located between each pair of modules. When any module is assigned an address, its adjacent adder will increment the address and assign the incremented address to the next-adjacent module.

A system of electronic modules is described, along with a method of assigning addresses to the modules. The modules are communicatively connected along a communication path, and are also communicatively connected to an address bus. Adders are positioned along the address bus, with at least one adder located between each pair of modules. When any module is assigned an address, its adjacent adder will increment the address and assign the incremented address to the next-adjacent module.

Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.

In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.