Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

Utilizing computing resources under a disabled processor node, including: identifying a disabled processor node, the disabled processor node representing a computer processor that is not being utilized for general purpose computer program instruction execution; identifying one or more computing resources that can be accessed only by the disabled processor node; and enabling a portion of the disabled processor node required to access the one or more computing resources.

A modular surgical system for use in a surgical procedure is disclosed. The modular surgical system includes a control module, a first surgical module arrangeable in a stack configuration with the control module, and a second surgical module arrangeable in a stack configuration with the control module and the first surgical module. The first surgical module includes a first counter module, a first stop-counter module configured to receive a sequence signal that causes the first stop-counter module to disable the first counter module from incrementing at a first final count, and a first delay module. The second surgical module includes a second counter module and a second stop-counter module configured to receive the sequence signal from the first surgical module after a predetermined delay. The sequence signal causes the second stop-counter module to disable the second counter module from incrementing at a second final count.

The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

An audio control system for a modular energy system. The audio control system can include a first controller and a second controller. The first controller can be configured to output an audio signal and an audio signal ID associated with the audio signal. The second controller can be coupled to the first controller and configured to receive the audio signal ID from the first controller and determine whether the audio signal ID corresponds to an expected audio signal ID.

A memory system includes a memory device configured to store a piece of data in a location which is distinguished by a physical address and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to transfer a response including the piece of map data to the external device.

When cascading interlockings of electronic locks, in particular for vaults, it is known to link all locks to a communications bus, wherein each lock has an associated serial number. Additionally, it is provided for additionally associating a sequential number to each lock so as to simplify managing the locks. Preferably, with a main lock, in which a translation table is stored, the sequential number of each lock in the system is associated to the serial number thereof; thereby, negotiating the numbers as follows: if two locks with the number 1 are connected to the communications bus, one lock keeps the number 1 and then adds a line in the translation table, in which a sequential number not yet assigned for the other lock and the serial number thereof are stored, and, if required, also adds all the locks not yet listed in the table.

An intra-device notational data movement system has a chassis including processing system(s) that are configured to provide a first thread and a second thread. A data mover subsystem in the chassis is coupled to the processing system(s). In a communication transmitted by the first thread, the data mover subsystem identifies a request to transfer data to the second thread that is stored in a first portion of a memory system that is associated with the first thread in a memory fabric management database. The data mover subsystem then modifies notational reference information in the memory fabric management database to disassociate the first portion of the memory system and the first thread and associate the first portion of the memory system with the second thread, which allows the second thread to reference the data using request/respond operations.

An operation method of a memory system includes a memory device including plural level memory cells. The operation method includes allocating a physical address according to a physical address allocation scheme which is determined based on an attribute of a write command; and performing a write operation on the allocated physical address.

In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.