A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

The present technology relates to an electronic device. A memory device having improved memory block management performance according to the present technology includes a memory block, a peripheral circuit, and a control logic. The peripheral circuit performs a read operation and a program operation on a selected physical page among a plurality of physical pages. The control logic controls the peripheral circuit to read first logical page data stored in a first physical page and second logical page data stored in a second physical page among the plurality of physical pages, and additionally program the second logical page data into the first physical page using the read first and second logical page data.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

A router device may receive, from a user device, a request for access to a file. The router device may determine that a cached version of the file is stored in a first data structure associated with the router device. The router device may communicate with a server device to determine whether the cached version of the file is current. The server device may be associated with a second data structure that stores a master version of the file. The router device may generate a copy of the cached version of the file based on communicating with the server device. The router device may send the copy of the cached version of the file to the user device.

An information processing apparatus including: a first management data storing region that stores a plurality of first links being provided one for each of multiple calculating cores and representing an order of migration of pages of a page group allocated to the calculating core among a plurality of the pages; a second management data storing region that stores a second link being provided for an operating system and managing a plurality of pages selected in accordance with the order of migration among the page group of the plurality of first links as a group of candidate pages to be migrated to the second memory; and a migration processor that migrates data of a page selected from the group of the second link from the first memory to the second memory. With this configuration, occurrence of a spinlock is reduced, so that the load on processor is reduced.

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric coupled to the system memory and the multiple vertical cache hierarchies. Based on a request of a requesting processor core among the plurality of processor cores, a master in the multiprocessor data processing system issues, via the interconnect fabric, a read-type memory access request. The master receives via the interconnect fabric at least one beat of conditional data issued speculatively on the interconnect fabric by a controller of the system memory prior to receipt by the controller of a systemwide coherence response for the read-type memory access request. The master forwards the at least one beat of conditional data to the requesting processor core.

Examples described herein relate to dynamically adjust a manner of identifying hot pages in a remote memory pool based on adjustment of parameters of a data structure. In some examples, the parameters of the data structure include a range of number of access counts and a number of pages associated with the range.

Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.

A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.

A method of failure mapping is provided. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.