A method includes saving a control state for a processor in response to commencing a transactional processing sequence, wherein saving the control state produces a saved control state. The method also includes permitting updates to the control state for the processor while executing the transactional processing sequence. Examples of updates to the control state include key mask changes, primary region table origin changes, primary segment table origin changes, CPU tracing mode changes, and interrupt mode changes. The method also includes restoring the control state for the processor to the saved control state in response to encountering a transactional error during the transactional processing sequence. In some embodiments, saving the control state comprises saving the current control state to memory corresponding to internal registers for an unused thread or another level of virtualization. A corresponding computer system and computer program product are also disclosed herein.

N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.

A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

Techniques are described herein for prediction of an buffer pool size (BPS). Before performing BPS prediction, gathered data are used to determine whether a target workload is in a steady state. Historical utilization data gathered while the workload is in a steady state are used to predict object-specific BPS components for database objects, accessed by the target workload, that are identified for BPS analysis based on shares of the total disk I/O requests, for the workload, that are attributed to the respective objects. Preference of analysis is given to objects that are associated with larger shares of disk I/O activity. An object-specific BPS component is determined based on a coverage function that returns a percentage of the database object size (on disk) that should be available in the buffer pool for that database object. The percentage is determined using either a heuristic-based or a machine learning-based approach.

Techniques are described herein for prediction of an buffer pool size (BPS). Before performing BPS prediction, gathered data are used to determine whether a target workload is in a steady state. Historical utilization data gathered while the workload is in a steady state are used to predict object-specific BPS components for database objects, accessed by the target workload, that are identified for BPS analysis based on shares of the total disk I/O requests, for the workload, that are attributed to the respective objects. Preference of analysis is given to objects that are associated with larger shares of disk I/O activity. An object-specific BPS component is determined based on a coverage function that returns a percentage of the database object size (on disk) that should be available in the buffer pool for that database object. The percentage is determined using either a heuristic-based or a machine learning-based approach.

A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.