A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are disclosed and claimed.

An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are disclosed and claimed.

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.