An information processing apparatus including: a first management data storing region that stores a plurality of first links being provided one for each of multiple calculating cores and representing an order of migration of pages of a page group allocated to the calculating core among a plurality of the pages; a second management data storing region that stores a second link being provided for an operating system and managing a plurality of pages selected in accordance with the order of migration among the page group of the plurality of first links as a group of candidate pages to be migrated to the second memory; and a migration processor that migrates data of a page selected from the group of the second link from the first memory to the second memory. With this configuration, occurrence of a spinlock is reduced, so that the load on processor is reduced.

Various implementations described herein relate to systems and methods for managing metadata for an atomic write operation, including determining metadata for data, queuing the metadata in an atomic list, in response to determining that atomic commit has occurred, moving the metadata from the atomic list to write lookup lists based on logical information of the data, and determining one of metadata pages of a non-volatile memory for each of the write lookup lists based on the logical information.

A data prefetching method and apparatus, and related storage device are provided. Data samples are collected. An AI chip trains the data samples to obtain a prefetching model. The AI chip then sends the prefetching model to a processor. The processor reads to-be-read data into a cache based on the prefetching model to reduce the computing burden of the processor.

Techniques are disclosed for managing metadata of a storage system. A storage control system receives data to be written to primary storage, and writes the received data together with metadata to a write cache. The storage control system destages the metadata from the write cache to a primary metadata structure which is configured to persistently store and index the metadata. The primary metadata structure comprises (i) a first data structure that is configured to accumulate the metadata destaged from the write cache and organize the accumulated metadata in blocks of metadata sorted by index keys, and (ii) a second data structure that is configured to receive the accumulated metadata from the first data structure, and organize the received metadata using an index structure that enables random-access to the metadata using the index keys.

Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.

A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.

A method, non-transitory computer readable medium, and device that assists with reducing memory fragmentation in solid state devices includes identifying an allocation area within an address range to write data from a cache. Next, the identified allocation area is determined for including previously stored data. The previously stored data is read from the identified allocation area when it is determined that the identified allocation area comprises previously stored data. Next, both the write data from the cache and the read previously stored data are written back into the identified allocation area sequentially through the address range.