Systems and methods for rules-based decisioning of events are disclosed. In one embodiment, a method may include: creating an in-memory cache by parsing stored checkpoints, signals, and rules definitions; receiving a checkpoint request; prioritizing the checkpoint request; preparing a basic context, comprising a limited set of objects, for the checkpoint request; using the in-memory cached definitions, generating at least one of a raw signal, an engineered signal, and a secondary signal for the checkpoint request based on the basic context; using the in-memory cached definitions, executing rules on at least one of the basic context, the raw signal, the engineered signal, and the secondary signal to generate a list of potential decisions; reducing the list of potential decisions to a list of final decisions; publishing the final decisions and supporting data rules and signals execution details; and executing the final decisions.

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, when updating a target firmware, a memory system may receive, from a host, a temporary firmware for increasing the size of a buffer from a preset first size to a second size equal to or greater than the size of the target firmware, may load and execute the temporary firmware into a processor, may receive the target firmware from the host and write the target firmware to the buffer, and may write the target firmware to the memory device.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, when updating a target firmware, a memory system may receive, from a host, a temporary firmware for increasing the size of a buffer from a preset first size to a second size equal to or greater than the size of the target firmware, may load and execute the temporary firmware into a processor, may receive the target firmware from the host and write the target firmware to the buffer, and may write the target firmware to the memory device.

Examples described herein include systems and methods for retaining information about bad memory pages across an operating system reboot. An example method includes detecting, by a first instance of an operating system, an error in a memory page of a non-transitory storage medium of a computing device executing the operating system. The operating system can tag the memory page as a bad memory page, indicating that the memory page should not be used by the operating system. The operating system can also store tag information indicating memory pages of the storage medium that are tagged as bad memory pages. The example method can also include receiving an instruction to reboot the operating system, booting a second instance of the operating system, and providing the tag information to the second instance of the operating system. The operating system can use the tag information to avoid using the bad memory pages.