A switched mode power supply comprises a communication interface including an address terminal configured to couple to an external resistor for setting a communication address of the switched mode power supply. A control circuit is configured to determine the value of the external resistor a first time with a first technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the first technique if the value of the external resistor is greater than the threshold value. The control circuit is also configured to, if the value of the external resistor is less than the threshold value, determine the value of the external resistor a second time with a second technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the second technique.

An information processing apparatus which is capable of being quickly started. In the information processing apparatus, a USB device is capable of being removably connected to a downstream port. In the information processing apparatus, at startup of the information processing apparatus, a setting process for making the USB device ready for use is started in a connecting state in which the USB device is connected to the downstream port, and when the setting process has been completed, whether or not the USB device is in the connecting state is detected.

A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.

A circuit for monitoring an output voltage of a voltage supply is shown. The circuit comprises a microcontroller for controlling a system, a shift register and a diagnostic circuit. The microcontroller has an input for receiving serial output data of the shift register, wherein the input is connected to the serial output of the shift register. The diagnostic circuit is designed to diagnose the voltage supply and has a diagnostic output which is connected to a data input of the shift register for inputting a diagnostic bit.

I/O network modules connect field devices to a process control network. Each I/O network module includes a set of electrical connectors for connecting a field device to the module and an I/O channel extending from the set of electrical connectors to a network port. The I/O channel includes a conversion circuit that converts between an I/O signal and network-compatible signals. Each I/O channel connected to the process control network through an I/O network module is associated with its own unique network address. This enables controllers and field devices on the process control network to communicate essentially directly with one another through the network.

Various embodiments provide a method performed by a handheld device and the handheld device, where a USB interface of the handheld device with an infrared remote control application is connected to a port of a display device by using an adapter cable, the handheld device determines that a preset source port of the display device is not the connected port, and automatically switches the source port to the connected port by using the infrared remote control application. The handheld device sends to-be-displayed content of the handheld device to the display device by using the USB interface, the adapter cable, and the connected port to enable the display device to display the to-be-displayed content.

The present invention relates to a data processing method, including the steps of intercepting a signal within a communications channel between a predefined peripheral device for a computing system and an application executing on the computing system and processing the signal and performing one or more actions in response to the processing. At least one action affects onward transmission of one or more signals within the communications channel. A data processing system is also described.

An audible beacon system includes an audible beacon chassis. A port connector is included on the audible beacon chassis and is configured to connect to a port on a computing device. An audible beacon device is coupled to the audible beacon chassis. An audible beacon driver device is included in the audible beacon chassis, is accessible via the port connector, and is configured to drive the audible beacon device to cause the audible beacon device to generate an audible sound. A storage device is included in the audible beacon chassis, is accessible via the port connector, and includes information that is configured to allow a computing device that is connected to the port connector to access the audible beacon driver device and cause the audible beacon driver device to drive the audible beacon device.

I/O network modules connect field devices to a process control network. Each I/O network module includes a set of electrical connectors for connecting a field device to the module and an I/O channel extending from the set of electrical connectors to a network port. The I/O channel includes a conversion circuit that converts between an I/O signal and network-compatible signals. Each I/O channel connected to the process control network through an I/O network module is associated with its own unique network address. This enables controllers and field devices on the process control network to communicate essentially directly with one another through the network.

Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.